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544EAEB001945BBGR PDF预览

544EAEB001945BBGR

更新时间: 2024-11-26 07:28:59
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
33页 1073K
描述
HCSL Output Clock Oscillator,

544EAEB001945BBGR 数据手册

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Ultra Series Crystal Oscillator  
Si544 Data Sheet  
Ultra Low Jitter I2C Programmable XO (150 fs), 0.2 to 1500 MHz  
The Si544 Ultra Seriesoscillator utilizes Silicon Laboratories’ advanced 4th  
generation DSPLL® technology to provide an ultra-low jitter, low phase noise  
clock at any output frequency. The device is user-programmed via simple  
I2C commands to provide any frequency from 0.2 to 1500 MHz with <1 ppb  
resolution and maintains exceptionally low jitter for both integer and fraction-  
al frequencies across its operating range. The Si544 offers excellent reliabili-  
ty and frequency stability as well as guaranteed aging performance. On-chip  
power supply filtering provides industry-leading power supply noise rejection,  
simplifying the task of generating low jitter clocks in noisy systems that use  
switched-mode power supplies. The Si544 has a dramatically simplified sup-  
ply chain that enables Silicon Labs to ship custom frequency samples 1-2  
weeks after receipt of order. Unlike a traditional XO, where a different crystal  
is required for each output frequency, the Si544 uses one simple crystal and  
a DSPLL IC-based approach to provide the desired output frequency. The  
Si544 is factory-configurable for a wide variety of user specifications, includ-  
ing startup frequency, I2C address, output format, and OE pin location/  
polarity. Specific configurations are factory-programmed at time of shipment,  
eliminating the long lead times associated with custom oscillators.  
KEY FEATURES  
• I2C programmable to any frequency from 0.2 to  
1500 MHz with < 1 ppb resolution  
• Very low jitter: 150 fs Typ RMS (12 kHz – 20 MHz)  
• Configure up to 4 pin-selectable startup frequencies  
• I2C interface supports 100 kbps, 400 kbps, and 1  
Mbps (Fast Mode Plus)  
• Excellent PSRR and supply noise immunity: –80  
dBc Typ  
• 3.3 V, 2.5 V and 1.8 V V supply operation from  
DD  
the same part number  
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual  
CMOS output options  
• 3.2x5, 5x7 mm package footprints  
• Samples available with 1-2 week lead times  
APPLICATIONS  
Pin Assignments  
SDA  
• 100G/200G/400G OTN, coherent optics, PAM4  
• 10G/40G/100G optical ethernet  
7
OE/FS/NC  
NC/OE/FS  
GND  
1
2
3
6
5
4
VDD  
• 3G-SDI/12G-SDI/24G-SDI broadcast video  
• Servers, switches, storage, search acceleration  
• Test and measurement  
CLK–  
CLK+  
8
• FPGA/ASIC clocking  
SCL  
(Top View)  
Fixed  
Frequency  
Crystal  
Frequency  
Flexible  
DSPLL  
Pin #  
Descriptions  
Selectable via ordering option  
Low  
Noise  
Driver  
DCO  
1, 2  
Digital  
Phase  
Detector  
Digital  
Loop  
Filter  
OSC  
Phase Error  
Cancellation  
OE = Output enable; FS = Frequency Select; NC = No connect  
Flexible  
Formats,  
Phase Error  
3
4
5
6
7
8
GND = Ground  
1.8V – 3.3V  
Operation  
Fractional  
Divider  
NVM  
Control  
CLK+ = Clock output  
Power Supply Regulation  
CLK- = Complementary clock output. Not used for CMOS.  
VDD = Power supply  
OE, Frequency Select  
(I2C and Pin Control)  
Built-in Power Supply  
Noise Rejection  
SDA = I2C Serial Data  
SCL = I2C Serial Clock  
silabs.com | Building a more connected world.  
Rev. 1.0  

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