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42S16400A PDF预览

42S16400A

更新时间: 2024-11-02 22:15:15
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
55页 469K
描述
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

42S16400A 数据手册

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®
IS42S16400A  
ISSI  
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
April 2003  
FEATURES  
OVERVIEW  
ISSI's64MbSynchronousDRAMIS42S16400Aisorganized  
as 1,048,576 bits x 16-bit x 4-bank for improved  
performance.ThesynchronousDRAMsachievehigh-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
• Clock frequency:166, 133, 100 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Single 3.3V power supply  
• LVTTL interface  
PIN CONFIGURATIONS  
54-Pin TSOP (Type II)  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
VCC  
I/O0  
VCCQ  
I/O1  
I/O2  
GNDQ  
I/O3  
I/O4  
VCCQ  
I/O5  
I/O6  
GNDQ  
I/O7  
VCC  
LDQM  
WE  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
GND  
I/O15  
GNDQ  
I/O14  
I/O13  
VCCQ  
I/O12  
I/O11  
GNDQ  
I/O10  
I/O9  
VCCQ  
I/O8  
GND  
NC  
• Programmable burst sequence:  
Sequential/Interleave  
2
3
4
5
• Self refresh modes  
6
7
• 4096 refresh cycles every 64 ms  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
• Burst read/write and burst read/single write  
operations capability  
UDQM  
CLK  
CKE  
NC  
CAS  
RAS  
CS  
• Burst termination by burst stop and precharge  
command  
BA0  
BA1  
A10  
A11  
A9  
A8  
• Byte controlled by LDQM and UDQM  
A0  
A7  
A1  
A6  
• Industrial temperature availability  
(133MHz, 100MHz)  
A2  
A5  
A3  
A4  
VCC  
GND  
• Package: 400-mil 54-pin TSOP II,  
a lead-free package is available.  
PIN DESCRIPTIONS  
WE  
WriteEnable  
A0-A11  
BA0, BA1  
I/O0 to I/O15  
CLK  
Address Input  
LDQM  
UDQM  
Vcc  
Lower Bye, Input/Output Mask  
Upper Bye, Input/Output Mask  
Power  
Bank Select Address  
Data I/O  
System Clock Input  
Clock Enable  
GND  
VccQ  
GNDQ  
NC  
Ground  
CKE  
Power Supply for I/O Pin  
Ground for I/O Pin  
NoConnection  
CS  
Chip Select  
RAS  
RowAddressStrobeCommand  
ColumnAddressStrobeCommand  
CAS  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liabilityarisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingon  
anypublishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
R e v . C  
1
04/16/03  

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