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403GC-3BA25C1 PDF预览

403GC-3BA25C1

更新时间: 2024-10-28 20:28:15
品牌 Logo 应用领域
AMCC 时钟外围集成电路
页数 文件大小 规格书
48页 768K
描述
RISC Microprocessor, 32-Bit, 25MHz, CMOS, PBGA160, PLASTIC, BGA-160

403GC-3BA25C1 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:160
Reach Compliance Code:unknown风险等级:5.39
Is Samacsys:N地址总线宽度:24
位大小:32边界扫描:YES
最大时钟频率:25 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:NO
JESD-30 代码:S-PBGA-B160长度:15 mm
低功率模式:YES端子数量:160
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:1.8 mm
速度:25 MHz最大供电电压:3.47 V
最小供电电压:3.14 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:15 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

403GC-3BA25C1 数据手册

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PowerPC 403GC  
32-Bit RISC  
Data  
Sheet  
Embedded Controller  
Overview  
Features  
The PowerPC 403GC 32-bit RISC embedded  
controller offers high performance and functional  
integration with low power consumption. The  
403GC RISC CPU executes at sustained speeds  
approaching one cycle per instruction. On-chip  
caches and integrated DRAM and SRAM control  
functions reduce chip count and design  
complexity in systems, while improving system  
throughput.  
PowerPC RISC CPU and instruction set  
architecture  
Glueless interfaces to DRAM, SRAM,  
ROM, and peripherals, including byte and  
half-word devices  
Separate instruction cache and write-back  
data cache, both two-way set-associative  
Memory management unit  
–64-entry, fully associative TLB array  
–Variable page size (1KB-16MB)  
–Flexible TLB management  
External I/O devices or SRAM/DRAM memory  
banks can be directly attached to the 403GC bus  
interface unit (BIU). Interfaces for up to eight  
memory banks and I/O devices, including a  
maximum of four DRAM banks, can be  
configured individually, allowing the BIU to  
manage devices or memory banks with differing  
control, timing, or bus width requirements.  
Individually programmable on-chip  
controllers for:  
Four DMA channels  
–DRAM, SRAM, and ROM banks  
–External interrupts  
Flexible interface to external bus masters  
Hardware multiplier and divider  
Thirty-two 32-bit general purpose registers  
Interrupt  
Timers  
Controller  
RISC Execution Unit  
Applications  
JTAG  
Port  
Set-top boxes  
Memory Management Unit  
Consumer electronics and video games  
Telecommunications and networking  
Office automation (printers, copiers, fax)  
Personal digital assistants (PDA)  
Instruction  
Cache Unit  
Data  
Cache Unit  
Serial  
Port  
4-Channel  
DMA  
Controller  
On-chip  
Peripheral  
Bus  
Specifications  
(Address  
and  
25MHz, 33MHz, and 40MHz versions  
Interfaces to both 3V and 5V technologies  
Control)  
Bus Interface Unit  
Low-power 3.3V operation with built-in  
power management and stand-by mode  
DRAM Controller  
I/O Controller  
Low-cost 160 lead PQFP package  
0.5 µm triple-level-metal CMOS  
SRAM, ROM, I/O  
Controls  
DRAM  
Controls  
Data Address  
Bus  
Bus  

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