Datasheet > 403GCX-3JC76C2

403GCX-3JC76C2

更新时间： 2024-10-27 23:21:19

品牌	Logo	应用领域
其他 - ETC		微处理器
页数	文件大小	规格书
54页	505K
描述
32-Bit Microprocessor

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403GCX-3JC76C2 数据手册

PowerPC 403GCX

32-Bit RISC

Data

Sheet

Embedded Controller

Overview

Features

The PowerPC 403GCX 32-bit RISC embedded

controller offers high performance and functional

integration with low power consumption. The

403GCX RISC CPU executes at sustained

speeds approaching one cycle per instruction.

On-chip caches and integrated DRAM and

SRAM control functions reduce chip count and

design complexity in systems, while improving

system throughput.

• PowerPC RISC CPU and instruction set

architecture

• Glueless interfaces to DRAM, SRAM,

ROM, and peripherals, including byte and

half-word devices

• 16KB instruction cache and 8KB write-

back data cache, two-way set-associative

• Memory management unit

–64-entry, fully associative TLB array

–Variable page size (1KB-16MB)

–Flexible TLB management

External I/O devices or SRAM/DRAM memory

banks can be directly attached to the 403GCX

bus interface unit (BIU). Interfaces for up to eight

memory banks and I/O devices, including a max-

imum of four DRAM banks, can be conﬁgured

individually, allowing the BIU to manage devices

or memory banks with differing control, timing, or

bus width requirements.

• Individually programmable on-chip control-

lers for:

–Four DMA channels

–DRAM, SRAM, and ROM banks

–External interrupts

• DRAM controller supports EDO DRAM

• Flexible interface to external bus masters

Interrupt

Timers

• CPU core can run at 2X the external bus

Controller

speed

RISC Execution Unit

JTAG

Port

Applications

Memory Management Unit

• Set-top boxes and network computers

• Consumer electronics and video games

• Telecommunications and networking

• Ofﬁce automation (printers, copiers, fax)

Instruction

Cache Unit

Data

Cache Unit

Serial

Port

4-Channel

DMA

Controller

On-chip

Peripheral

Bus

Speciﬁcations

(Address

• CPU core frequency of 76 MHz, I/Os to

and

Control)

38 MHz

• Interfaces to both 3V and 5V technologies

Bus Interface Unit

• Low-power 3.3V operation with built-in

DRAM Controller

I/O Controller

power management and stand-by mode

• Low-cost 160 lead PQFP package

• 0.45 µm triple-level-metal CMOS

SRAM, ROM, I/O

Controls

DRAM

Controls

Data Address

Bus

12 3 4 5 6 7...54

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