3D7408
Ò
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7408)
data
delay
3
devices, inc.
PACKAGES
FEATURES
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All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
IN
AE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
SO/P0
P1
Low ground bounce noise
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
P2
P6
Leading- and trailing-edge accuracy
Increment range: 0.25 through 5.0ns
Delay tolerance: 1% (See Table 1)
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±1% typical (4.75V-5.25V)
Minimum input pulse width: 10% of total
delay
P3
SC
P5
P4
GND
SI
SI
3D7408S
SOIC
(300 Mil)
3D7408 DIP
3D7408G Gull Wing
(300 Mil)
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Programmable via 3-wire serial or 8-bit
parallel interface
(For mechanical data, see Case Dimensions document)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7408 Programmable 8-Bit Silicon Delay Line product
family consists of 8-bit, user-programmable CMOS silicon
integrated circuits. Delay values, programmed either via the
serial or parallel interface, can be varied over 255 equal steps
ranging from 250ps to 5.0ns inclusively. Units have a typical
inherent (zero step) delay of 12ns to 17ns (See Table 1). The
input is reproduced at the output without inversion, shifted in time
as per user selection. The 3D7408 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features
both rising- and falling-edge accuracy.
IN
Signal Input
OUT Signal Output
MD
AE
P0-P7 Parallel Data Input
SC
SI
Mode Select
Address Enable
Serial Clock
Serial Data Input
Serial Data Output
SO
VCC +5 Volts
GND Ground
The all-CMOS 3D7408 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
DELAYS AND TOLERANCES
INPUT RESTRICTIONS
Step 0
Delay (ns)
12 ± 2
12 ± 2
12 ± 2
14 ± 2
17 ± 2
17 ± 2
17 ± 2
Step 255
Delay
Max Operating
Absolute Max Min Operating
Absolute Min
Oper P.W.
5.5 ns
NUMBER
Delay (ns)
75.75 ± 4.0
139.5 ± 4.0
267.0 ± 5.0
522.0 ± 6.0
782.0 ± 8.0
1037 ± 9.0
1292 ± 10
Increment (ns) Frequency
Oper Freq
P.W.
3D7408-0.25
3D7408-0.5
3D7408-1
3D7408-2
3D7408-3
3D7408-4
3D7408-5
6.25 MHz
90 MHz
80.0 ns
160.0 ns
320.0 ns
640.0 ns
960.0 ns
1280.0 ns
1600.0 ns
0.25 ± 0.15
0.50 ± 0.25
1.00 ± 0.50
2.00 ± 1.00
3.00 ± 1.50
4.00 ± 2.00
5.00 ± 2.50
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
45 MHz
22 MHz
11 MHz
7.5 MHz
5.5 MHz
4.4 MHz
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.
All delays referenced to input pin
Ó1996 Data Delay Devices
Doc #96003
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1