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3D7105K-1 PDF预览

3D7105K-1

更新时间： 2024-09-16 02:51:03
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DATADELAY /
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4页 36K
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MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105)

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3D7105  
Ò
MONOLITHIC 5-TAP  
FIXED DELAY LINE  
(SERIES 3D7105)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
IN  
O2  
O4  
1
2
3
4
8
7
6
5
VDD  
O1  
O3  
·
·
·
All-silicon, low-power CMOS  
technology  
TTL/CMOS compatible  
inputs and outputs  
Vapor phase, IR and wave  
solderable  
Auto-insertable (DIP pkg.)  
Low ground bounce noise  
IN  
O2  
VDD  
IN  
N/C  
N/C  
O2  
VDD  
N/C  
O1  
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
O1  
O3  
O5  
GND  
O5  
O4  
3D7105Z  
SOIC  
(150 Mil)  
GND  
N/C  
O3  
N/C  
O4  
3D7105M DIP  
3D7105H Gull-Wing  
(300 Mil)  
·
·
·
·
·
·
·
·
·
N/C  
O5  
GND  
8
Leading- and trailing-edge accuracy  
Delay range: .75 through 80ns  
Delay tolerance: 5% or 1ns  
Temperature stability: ±3% typical (0C-70C)  
Vdd stability: ±1% typical (4.75V-5.25V)  
Minimum input pulse width: 30% of total delay  
14-pin DIP and 16-pin SOIC available as drop-in  
replacements for hybrid delay lines  
3D7105 DIP  
IN  
N/C  
N/C  
O2  
N/C  
O4  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
N/C  
N/C  
O1  
N/C  
O3  
3D7105G Gull-Wing  
3D7105K Unused pins  
removed  
(300 Mil)  
N/C  
GND  
N/C  
O5  
3D7105S SOIC  
(300 Mil)  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
IN  
Delay Line Input  
The 3D7105 5-Tap Delay Line product family consists of fixed-delay  
CMOS integrated circuits. Each package contains a single delay line,  
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap  
(incremental) delay values can range from 0.75ns through 8.0ns. The  
input is reproduced at the outputs without inversion, shifted in time as per  
the user-specified dash number. The 3D7105 is TTL- and CMOS-  
compatible, capable of driving ten 74LS-type loads, and features both  
rising- and falling-edge accuracy.  
O1  
O2  
O3  
O4  
O5  
Tap 1 Output (20%)  
Tap 2 Output (40%)  
Tap 3 Output (60%)  
Tap 4 Output (80%)  
Tap 5 Output (100%)  
VCC +5 Volts  
GND Ground  
N/C No Connection  
The all-CMOS 3D7105 integrated circuit has been designed as a reliable,  
economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP  
and a space saving surface mount 8-pin SOIC.  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART NUMBER  
TOLERANCES  
INPUT RESTRICTIONS  
DIP-8  
3D7105M  
3D7105H  
SOIC-8  
3D7105Z  
DIP-14  
3D7105  
3D7105G  
3D7105K  
SOIC-16  
3D7105S  
TOTAL  
DELAY (ns)  
TAP-TAP  
DELAY  
(ns)  
Max  
Operating  
Frequency  
Absolute  
Max  
Oper. Freq.  
Min  
Operating  
Pulse Width  
Absolute  
Min  
Oper. P.W.  
-.75  
-1  
-1.5  
-2  
-2.5  
-4  
-5  
-.75  
-1  
-1.5  
-2  
-2.5  
-4  
-5  
-.75  
-1  
-1.5  
-2  
-2.5  
-4  
-5  
-.75  
-1  
-1.5  
-2  
-2.5  
-4  
-5  
41.7 MHz  
37.0 MHz  
30.3 MHz  
25.6 MHz  
22.2 MHz  
15.9 MHz  
13.3 MHz  
9.52 MHz  
166.7 MHz  
166.7 MHz  
166.7 MHz  
166.7 MHz  
133.3 MHz  
83.3 MHz  
66.7 MHz  
41.7 MHz  
12.0 ns  
13.5 ns  
16.5 ns  
19.5 ns  
22.5 ns  
31.5 ns  
37.5 ns  
52.5 ns  
3.00 ns  
3.00 ns  
3.00 ns  
3.00 ns  
3.75 ns  
6.00 ns  
7.50 ns  
12.0 ns  
3.0 ± 1.0*  
4.0 ± 1.0*  
6.0 ± 1.0*  
8.0 ± 1.0*  
10.0 ± 1.0*  
16.0 ± 1.0*  
25.0 ± 1.3  
40.0 ± 2.0  
0.75 ± 0.4  
1.0 ± 0.5  
1.5 ± 0.7  
2.0 ± 0.8  
2.5 ± 1.0  
4.0 ± 1.3  
5.0 ± 1.5  
8.0 ± 1.5  
-8  
-8  
-8  
-8  
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns  
NOTE: Any dash number between .75 and 8 not shown is also available.  
Ó1996 Data Delay Devices  
Doc #96006  
12/2/96  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

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