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3D7010SERIES

更新时间： 2024-09-14 23:21:07
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MONOLITHIC 10-TAP FIXED DELAY LINE

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3D7010SERIES 数据手册

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3D7010  
Ò
MONOLITHIC 10-TAP  
FIXED DELAY LINE  
(SERIES 3D7010)  
data  
delay  
3
devices, inc.  
PACKAGES  
FEATURES  
·
·
·
·
·
·
·
·
·
·
·
All-silicon, low-power CMOS technology*  
TTL/CMOS compatible inputs and outputs  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP package)  
Low ground bounce noise  
Leading- and trailing-edge accuracy  
Delay range: 8 through 500ns  
IN  
N/C  
O2  
VDD  
O1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
O3  
IN  
N/C  
N/C  
O2  
O4  
O6  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
N/C  
O1  
O3  
O5  
O7  
O9  
O10  
O4  
O5  
O6  
O7  
O8  
O9  
O8  
GND  
GND  
O10  
8
Delay tolerance: 5% or 2ns  
Temperature stability: ±3% typical (0C-70C)  
Vdd stability: ±2% typical (4.75V-5.25V)  
Minimum input pulse width: 20% of total  
delay  
3D7010S  
SOIC  
(300 Mil)  
3D7010 DIP  
3D7010G Gull-Wing  
(300 Mil)  
(For mechanical data, see Case Dimensions document)  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D7010 10-Tap Delay Line product family consists of fixed-delay  
CMOS integrated circuits. Each package contains a single delay line,  
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap  
(incremental) delay values can range from 8ns through 50ns. The input  
is reproduced at the outputs without inversion, shifted in time as per the  
user-specified dash number. The 3D7010 is TTL- and CMOS-  
compatible, capable of driving ten 74LS-type loads, and features both  
rising- and falling-edge accuracy.  
IN  
Delay Line Input  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
O8  
O9  
Tap 1 Output (10%)  
Tap 2 Output (20%)  
Tap 3 Output (30%)  
Tap 4 Output (40%)  
Tap 5 Output (50%)  
Tap 6 Output (60%)  
Tap 7 Output (70%)  
Tap 8 Output (80%)  
Tap 9 Output (90%)  
The all-CMOS 3D7010 integrated circuit has been designed as a  
reliable, economic alternative to hybrid TTL fixed delay lines. It is  
offered in a standard 14-pin auto-insertable DIP and a space saving  
surface mount 16-pin SOIC.  
O10 Tap 10 Output (100%)  
VCC +5 Volts  
GND Ground  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART NUMBER  
TOLERANCES  
INPUT RESTRICTIONS  
Max Operating Absolute Max Min Operating  
DIP-14  
3D7010  
3D7010G  
-80  
SOIC-16  
3D7010S  
TOTAL  
DELAY  
(ns)  
TAP-TO-TAP  
DELAY  
Absolute Min  
Oper. P.W.  
Frequency  
Oper. Freq.  
Pulse Width  
(ns)  
-80  
4.17 MHz  
3.70 MHz  
3.33 MHz  
2.22 MHz  
1.67 MHz  
1.33 MHz  
1.11 MHz  
0.83 MHz  
0.67 MHz  
31.2 MHz  
27.8 MHz  
25.0 MHz  
16.7 MHz  
12.5 MHz  
10.0 MHz  
8.33 MHz  
6.25 MHz  
5.00 MHz  
120.0 ns  
135.0 ns  
150.0 ns  
225.0 ns  
300.0 ns  
375.0 ns  
450.0 ns  
600.0 ns  
750.0 ns  
16.0 ns  
18.0 ns  
20.0 ns  
30.0 ns  
40.0 ns  
50.0 ns  
60.0 ns  
80.0 ns  
100.0 ns  
80 ± 4.0  
90 ± 4.5  
8.0 ± 1.5  
9.0 ± 1.7  
10.0 ± 2.0  
15.0 ± 2.0  
20.0 ± 2.5  
25.0 ± 2.5  
30.0 ± 3.0  
40.0 ± 4.0  
50.0 ± 5.0  
-90  
-90  
-100  
-150  
-200  
-250  
-300  
-400  
-500  
-100  
-150  
-200  
-250  
-300  
-400  
-500  
100 ± 5.0  
150 ± 7.5  
200 ± 10.0  
250 ± 12.5  
300 ± 15.0  
400 ± 20.0  
500 ± 25.0  
NOTE: Any dash number between 80 and 500 not shown is also available.  
*PATENTED  
Ó1996 Data Delay Devices  
Doc #96004  
12/2/96  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

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