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348R-XXLFT PDF预览

348R-XXLFT

更新时间: 2024-09-16 20:58:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 103K
描述
Clock Generator, 200MHz, CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20

348R-XXLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.68
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:8.65 mm端子数量:20
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

348R-XXLFT 数据手册

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DATASHEET  
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER  
ICS348  
Description  
Features  
The ICS348 field programmable clock synthesizer  
generates up to 9 high-quality, high-frequency clock outputs  
including multiple reference clocks from a low frequency  
crystal or clock input. The ICS348 has 4 independent  
on-chip PLLs and is designed to replace crystals and  
crystal oscillators in most electronic systems.  
Packaged as 20-pin SSOP (QSOP) (Pb-free)  
Eight addressable registers  
Replaces multiple crystals and oscillators  
Output frequencies up to 200 MHz at 3.3V  
Input crystal frequency of 5 to 27 MHz  
Input clock frequency of 2 to 50 MHz  
Up to nine reference outputs  
TM  
Using IDT’s VersaClock software to configure PLLs and  
outputs, the ICS348 contains a One-Time Programmable  
(OTP) ROM to allow field programmability. Programming  
features include eight selectable configuration registers, up  
to two sets of four low-skew outputs.  
Up to two sets of four low-skew outputs  
Operating voltages of 3.3 V  
Using Phase-Locked Loop (PLL) techniques, the device  
runs from a standard fundamental mode, inexpensive  
crystal, or clock. It can replace multiple crystals and  
oscillators, saving board space and cost.  
Advanced, low power CMOS process  
For one output clock, use the ICS341 (8-pin). For two  
output clocks, use the ICS342 (8-pin). For three output  
clocks, use the ICS343 (8-pin). For more than three  
outputs, use the ICS345 or ICS348.  
The ICS348 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
3
VDD  
CLK1  
CLK2  
PLL1  
OTP  
ROM  
with  
PLL  
S2:S0  
3
CLK3  
PLL2  
PLL3  
PLL4  
Divide  
Logic  
and  
Output  
Enable  
Control  
Values  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
X2  
GND  
2
External capacitors are  
required with a crystal input.  
PDTS  
IDT® QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER  
1
ICS348  
REV N 090613  

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