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32F8030-CN PDF预览

32F8030-CN

更新时间: 2024-09-21 06:24:51
品牌 Logo 应用领域
其他 - ETC 电子
页数 文件大小 规格书
10页 65K
描述
Programmable Electronic Filter

32F8030-CN 数据手册

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SSI 32F8030  
Programmable  
Electronic Filter  
A TDK Group Company  
April 1995  
DESCRIPTION  
FEATURES  
The SSI 32F8030 Programmable Electronic Filter pro-  
vides an electronically controlled low–pass filter with a  
separate differentiated low–pass output. A seven–  
pole, 0.05° Equiripple-type linear phase, low–pass  
filter is provided along with a single-pole, single-zero  
differentiator. Both outputs have matched delays. The  
delay matching is unaffected by any amount of pro-  
grammed high frequency peaking (boost) or band-  
width. This programability, combined with low group  
delay variation makes the SSI 32F8030 ideal for use in  
many applications. Double differentiation high fre-  
quency boost is accomplished by a two–pole, low–  
pass with a two–pole, high–pass feed forward section  
to provide complementary real axis zeros. A variable  
attenuator is used to program the zero locations, which  
controls the amount of boost.  
Ideal for:  
- constant density recording applications  
- magnetic tape recording  
Programmable filter cutoff frequency  
(ƒc = 250 kHz to 2.5 MHz)  
Programmable high frequency peaking  
(0 to 9 dB boost at the filter cutoff frequency)  
Matched normal and differentiated low-pass  
outputs  
Differential filter input and outputs  
±3.0% group delay variation from  
0.2 ƒc to 1.75 ƒc, 0.25 MHz ƒc 2.5 MHz  
Total harmonic distortion less than 1%  
+5V only operation  
The SSI 32F8030 programmable boost and bandwidth  
characteristics can be controlled by external DACs or  
DACs provided in the SSI 32D4661 Time Base Gen-  
erator. Fixed characteristics are easily accomplished  
with three external resistors. In addition, boost can be  
switched in or out by a logic signal.  
16-Lead SON, and SOL packages  
5 mW idle mode  
The SSI 32F8030 requires only a +5V supply and is  
available in 16-Lead SON, and SOL packages.  
BLOCK DIAGRAM  
PIN DIAGRAM  
VO_NORM+  
VIN+  
VIN-  
Low Pass  
Filter  
Low Pass  
Filter  
GND1  
VO_NORM-  
VO_NORM+  
VCC1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VO_DIFF+  
VO_DIFF-  
PWRON  
VR  
Summer  
VO_NORM-  
VO_DIFF+  
VO_DIFF-  
High Pass  
Filter  
Variable  
Atten.  
High Pass  
Filter  
VIN-  
VCC2  
IFP  
VIN+  
VBP  
VFP  
VBP  
IFP  
FBST  
GND2  
VREF  
BIAS  
VR  
Filter  
Control  
VFP  
PWRON  
FBST  
GND1  
GND2  
VCC1  
VCC2  
CAUTION: Use handling procedures necessary  
for a static sensitive component.  
1
04/14/95 - rev.  

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