Datasheet > 2N5900

2N5900

更新时间： 2024-11-01 23:19:51

品牌	Logo	应用领域
其他 - ETC		晶体晶体管
页数	文件大小	规格书
20页	1041K
描述
TRANSISTOR \| BJT \| PNP \| 60V V(BR)CEO \| 7A I(C) \| TO-66

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2N5900 数据手册

CY7C1339

128K x 32 Synchronous-Pipelined Cache RAM

The CY7C1339 I/O pins can operate at either the 2.5V or the

Features

3.3V level; the I/O pins are 3.3V tolerant when V

=2.5V.

DDQ

• Supports 100-MHz bus for Pentium and PowerPC™

operations with zero wait states

• Fully registered inputs and outputs for pipelined oper-

ation

• 128K by 32 common I/O architecture

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.5 ns (166-MHz

device).

The CY7C1339 supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The burst

sequence is selected through the MODE pin. Accesses can

be initiated by asserting either the Processor Address Strobe

(ADSP) or the Controller Address Strobe (ADSC) at clock rise.

Address advancement through the burst sequence is con-

trolled by the ADV input. A 2-bit on-chip wraparound burst

counter captures the first address in a burst sequence and

automatically increments the address for the rest of the burst

access.

• User-selectable burst counter supporting Intel Pen-

tium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Byte write operations are qualified with the four Byte Write

Select (BW

) inputs. A Global Write Enable (GW) overrides

• JEDEC-standard 100 TQFP pinout

[3:0]

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

Three synchronous Chip Selects (CE , CE , CE ) and an

The CY7C1339 is a 3.3V, 128K by 32 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

MODE

Logic Block Diagram

)

[1;0]

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

128KX32

MEMORY

ARRAY

[16:0]

DQ[31:24]

BYTEWRITE

REGISTERS

BWE

DQ[23:16]

BYTEWRITE

REGISTERS

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

OUTPUT

REGISTERS

CLK

INPUT

REGISTERS

CLK

ENABLE DELAY

CLK

SLEEP

CONTROL

[31:0]

Intel and Pentium are trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

May 8, 2000

12 3 4 5 6 7...20

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与2N5900相关器件

型号	品牌	获取价格	描述	数据表
2N5901	ETC	获取价格	TRANSISTOR \| BJT \| PNP \| 25V V(BR)CEO \| 7A I(C) \| TO-66
2N5902	INTERSIL	获取价格	MONOLITHIC DUAL N CHANNEL JFET GENERAL PURPOSE AMPLIFIER
2N5902	NJSEMI	获取价格	DUAL N-CHANNEL FETS
2N5903	INTERSIL	获取价格	MONOLITHIC DUAL N CHANNEL JFET GENERAL PURPOSE AMPLIFIER
2N5904	INTERSIL	获取价格	MONOLITHIC DUAL N CHANNEL JFET GENERAL PURPOSE AMPLIFIER
2N5904	NJSEMI	获取价格	DUAL N-CHANNEL FETS
2N5905	INTERSIL	获取价格	MONOLITHIC DUAL N CHANNEL JFET GENERAL PURPOSE AMPLIFIER
2N5905	NJSEMI	获取价格	DUAL N-CHANNEL JFET
2N5905	MICROSS	获取价格	LOW NOISE, LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET
2N5905_TO-78	MICROSS	获取价格	LOW NOISE, LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET

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