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11274-001-XTD PDF预览

11274-001-XTD

更新时间: 2024-11-11 14:38:59
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
43页 1343K
描述
PLL FREQUENCY SYNTHESIZER, 28MHz, PDSO16, 0.150 INCH, SOIC-16

11274-001-XTD 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.71Is Samacsys:N
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.89 mm
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.73 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

11274-001-XTD 数据手册

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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC  
Data Sheet  
1.0 Features  
Complete programmable control via I2C™-bus  
Selectable CMOS or PECL compatible outputs  
External feedback loop capability allows genlocking  
Tunable VCXO loop for jitter attenuation  
2.0 Description  
The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of  
electronic systems. Via the I2C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.  
The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their  
granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock  
generator available.  
3.0 Applications  
Frequency synthesis  
Line-locked and genlock applications  
Clock multiplication  
Telecom jitter attenuation  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SCL  
SDA  
CLKN  
CLKP  
VDD  
ADDR  
VSS  
FBK  
XIN  
REF  
XOUT  
XTUNE  
VDD  
VSS  
EXTLF  
LOCK/IPRG  
16-pin 0.150" SOIC  
Figure 1: Pin Configuration  
AMI Semiconductor – Rev. 3.0, Jan. 08  
www.amis.com Specifications subject to change without notice  
1

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