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11274-901

更新时间: 2024-11-11 06:23:23
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其他 - ETC 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
39页 435K
描述
Programmable Line Lock Clock Generator IC

11274-901 数据手册

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FS6131-01  
Programmable Line Lock Clock Generator IC  
1.0  
Features  
3.0  
Applications  
2
ä
Complete programmable control via I C -bus  
Selectable CMOS or PECL compatible outputs  
External feedback loop capability allows genlocking  
Tunable VCXO loop for jitter attenuation  
Frequency Synthesis  
Line-Locked and Genlock Applications  
Clock Multiplication  
Telecom Jitter Attenuation  
Commercial (FS6131-01) and industrial (FS6131-01i)  
temperature versions available  
Figure 1: Pin Configuration  
1
2
3
4
5
6
7
8
16  
SCL  
SDA  
CLKN  
CLKP  
VDD  
2.0  
Description  
15  
14  
13  
12  
11  
10  
9
The FS6131-01 is a monolithic CMOS clock genera-  
tor/regenerator IC designed to minimize cost and compo-  
nent count in a variety of electronic systems. Via the I2C-  
bus interface, the FS6131-01 can be adapted to many  
clock generation requirements.  
ADDR  
VSS  
FBK  
XIN  
REF  
XOUT  
XTUNE  
VDD  
VSS  
The ability to tune the on-board voltage-controlled crystal  
oscillator (VCXO), the length of the Reference and Feed-  
back Dividers, their granularity, and the flexibility of the  
Post Divider make the FS6131-01 the most flexible  
stand-alone phase-locked loop (PLL) clock generator  
available.  
EXTLF  
LOCK/IPRG  
16-pin 0.150" SOIC  
Figure 2: Block Diagram  
LFTC  
CLF  
CLP  
XTUNE  
(optional)  
Control  
ROM  
XLROM[2:0]  
CRYSTAL LOOP  
Internal  
Loop  
Filter  
XCT[3:0],  
XLVTEN  
RLF  
XLPDEN,  
XLSWAP  
XLCP[1:0]  
XIN  
VCXO  
Divider  
0
1
EXTLF  
UP  
VCXO  
Phase-  
Frequency  
Detector  
(optional)  
Charge  
Pump  
EXTLF  
XOUT  
(optional)  
STAT[1:0]  
DOWN  
CMOS  
Lock  
Detect  
1
0
LOCK/  
IPRG  
REFDIV[11:0]  
(optional)  
POST3[1:0]  
POST2[1:0]  
POST1[1:0]  
REF  
VCOSPD,  
OSCTYPE  
0
GBL  
Reference  
Divider  
(NR)  
MLCP[1:0]  
(fREF  
)
PDREF  
0
1
11  
REFDSRC  
UP  
CLKP  
Post  
Divider  
01  
00  
Phase-  
Frequency  
Detector  
Voltage  
Controlled  
Oscillator  
Clock  
Gobbler  
Charge  
Pump  
1
1
(fCLK  
)
(NPx  
)
10  
CLKN  
FBK  
DOWN  
0
CMOS/PECL  
Output  
OUTMUX[1:0]  
PDFBK  
11  
(fVCO  
)
ADDR  
01  
10  
00  
Feedback  
Divider (NF)  
SCL  
SDA  
FBKDSRC[1:0]  
I2C  
Interface  
MAIN LOOP  
Registers  
FBKDIV[13:0]  
FS6131  
I2C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail  
specifications as may be required to permit improvements in the design of its products.  

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