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11274-901-XTP PDF预览

11274-901-XTP

更新时间: 2024-11-11 14:38:59
品牌 Logo 应用领域
安森美 - ONSEMI 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
43页 1343K
描述
230MHz, OTHER CLOCK GENERATOR, PDSO16, 0.150 INCH, SOIC-16

11274-901-XTP 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.76
JESD-30 代码:R-PDSO-G16长度:9.9 mm
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:230 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
主时钟/晶体标称频率:28 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

11274-901-XTP 数据手册

 浏览型号11274-901-XTP的Datasheet PDF文件第2页浏览型号11274-901-XTP的Datasheet PDF文件第3页浏览型号11274-901-XTP的Datasheet PDF文件第4页浏览型号11274-901-XTP的Datasheet PDF文件第5页浏览型号11274-901-XTP的Datasheet PDF文件第6页浏览型号11274-901-XTP的Datasheet PDF文件第7页 
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC  
Data Sheet  
1.0 Features  
Complete programmable control via I2C™-bus  
Selectable CMOS or PECL compatible outputs  
External feedback loop capability allows genlocking  
Tunable VCXO loop for jitter attenuation  
2.0 Description  
The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of  
electronic systems. Via the I2C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.  
The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their  
granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock  
generator available.  
3.0 Applications  
Frequency synthesis  
Line-locked and genlock applications  
Clock multiplication  
Telecom jitter attenuation  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SCL  
SDA  
CLKN  
CLKP  
VDD  
ADDR  
VSS  
FBK  
XIN  
REF  
XOUT  
XTUNE  
VDD  
VSS  
EXTLF  
LOCK/IPRG  
16-pin 0.150" SOIC  
Figure 1: Pin Configuration  
AMI Semiconductor – Rev. 3.0, Jan. 08  
www.amis.com Specifications subject to change without notice  
1

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