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100LVEL11M8 PDF预览

100LVEL11M8

更新时间: 2024-09-16 22:16:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 134K
描述
3.3V ECL 1:2 Differential Fanout Buffer

100LVEL11M8 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.76其他特性:NECL MODE:VCC=0V WITH VEE=-3V TO -3.8V
系列:100LVEL输入调节:DIFFERENTIAL
JESD-30 代码:S-PDSO-G8长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:-3.3 VProp。Delay @ Nom-Sup:0.435 ns
传播延迟(tpd):0.405 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.02 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL100K
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:3 mm最小 fmax:1000 MHz
Base Number Matches:1

100LVEL11M8 数据手册

 浏览型号100LVEL11M8的Datasheet PDF文件第2页浏览型号100LVEL11M8的Datasheet PDF文件第3页浏览型号100LVEL11M8的Datasheet PDF文件第4页浏览型号100LVEL11M8的Datasheet PDF文件第5页浏览型号100LVEL11M8的Datasheet PDF文件第6页 
January 2003  
Revised January 2003  
100LVEL11  
3.3V ECL 1:2 Differential Fanout Buffer  
General Description  
Features  
The 100LVEL11 is a low voltage 1:2 differential fanout  
buffer. One differential input signal is fanned out to two  
identical differential outputs. By supplying a constant refer-  
ence level to one input pin a single ended input condition is  
created.  
Typical propagation delay of 330 ps  
Typical IEE of 24 mA  
Typical skew of 5 ps between outputs  
Internal pull-down resistors on D  
Fairchild MSOP-8 package is a drop-in replacement to  
ON TSSOP-8  
With inputs Open or both inputs at VEE, the differential Q  
outputs default LOW and Q outputs default HIGH.  
The 100 series is temperature compensated.  
Meets or exceeds JEDEC specification EIA/JESD78 IC  
latch-up tests  
Moisture Sensitivity Level 1  
ESD Performance:  
Human Body Model > 2000V  
Machine Model > 200V  
Ordering Code:  
Package Product  
Order Number  
Number  
Code  
Package Description  
Top Mark  
100LVEL11M  
M08A  
KVL11 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
KV11 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide  
100LVEL11M8  
(Preliminary)  
MA08D  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Top View  
Pin Descriptions  
Pin Name  
Description  
Q0, Q0, Q1, Q1  
ECL Data Outputs  
D, D  
VCC  
VEE  
ECL Data Inputs  
Positive Supply  
Negative Supply  
© 2003 Fairchild Semiconductor Corporation  
DS500775  
www.fairchildsemi.com  

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