Datasheet > ZSSC3026KIT

ZSSC3026KIT

更新时间： 2022-02-26 11:18:05

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
51页	710K
描述
Low Power, High Resolution 16-Bit Sensor Signal Conditioner

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ZSSC3026KIT 数据手册

ZSSC3026

In order to achieve minimum current consumption in idle mode, a dynamic power-on-reset circuit is implemented.

The V_DDlow level and the subsequent rise time and V_DDrising slope must fulfill specific constraints to guarantee

an overall ZSSC3026 reset. In general, lower V_DDlow levels allow slower rising of the subsequent on-ramp of V_DD.

The following table shows the relevant reset parameters and conditions. Other combinations might also be

possible. For example, the reset trigger can be influenced by increasing the power-down time and relaxing the

V_DDrising slope requirement.

Table 1.3 Constraints for VDD Power-On Reset

PARAMETER

SYMBOL

t_SPIKE

MIN

TYP

MAX

UNIT

µs

Power Down Time (duration of VDD Low Level)

V_DDLow Level

0.2

VDD_LOW

SR_VDD

V_DDRising Slope

V/ms

1.3. Electrical Parameters

All parameter values are valid only under specified operating conditions. All voltages are referenced to V_SS.

Table 1.4 Electrical Parameters

PARAMETER

SYMBOL

V_DDB

CONDITIONS/COMMENTS

SUPPLY

MIN

TYP

MAX

UNIT

Bridge Supply Voltage,

ADC Reference Voltage

Internally generated

1.60

1.67

1.74

Active State, average

900

1500

250

µA

Sleep State, idle current, <85°C

Sleep State, idle current, <125°C

Current Consumption

I_VDD

950

Power Supply Rejection

(see section 1.4)

V_DD= 1.8V

PSR_VDD

V_DD= 2V

20·log₁₀(V_DD/V_DDB

)

Memory Program Voltage

Mean Program Current

V_DD,prog

I_VDD,Prog

Required voltage level at VDD pin

2.9

3.6

Mean current consumption during

MTP programming cycle at VDD

MTP Program at VDD pin,

dynamic switch-on current draw

Peak Program Current

I_prog,max

March 28, 2016

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