Datasheet > ZL50064

ZL50064

更新时间： 2024-02-25 15:25:53

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		开关
页数	文件大小	规格书
68页	887K
描述
16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs

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技术参数
数据手册

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ZL50064 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LFQFP, QFP256,1.2SQ,16	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.61	JESD-30 代码：	S-PQFP-G256
JESD-609代码：	e0	长度：	28 mm
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP256,1.2SQ,16	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	225
电源：	1.8,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Other Telecom ICs
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.4 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	28 mm
Base Number Matches：	1

ZL50064 数据手册

ZL50062/4

Data Sheet

Pin Description

Pin Name

ZL50064

Package

Coordinates

(256-pin

ZL50062

Package

Coordinates

(256-ball

PBGA)

Description

LQFP)

Device Timing

C8i

T10

Master Clock (5V Tolerant Schmitt-Triggered Input). This

pin accepts an 8.192MHz clock. The internal frame boundary

is aligned with the clock falling or rising edge, as controlled by

the C8IPOL bit in the Control Register. Input data on both the

Backplane and Local sides (BSTi0-31 and LSTi0-31) must be

aligned to this clock and the accompanying input frame pulse,

FP8i.

FP8i

R11

Frame Pulse Input (5V Tolerant Schmitt-Triggered Input).

When the Frame Pulse Width bit (FPW) of the Control

frame pulse. When the FPW bit is HIGH, this pin accepts a

244ns-wide frame pulse. The device will automatically detect

whether an ST-BUS or GCI-Bus style frame pulse is applied.

Input data on both the Backplane and Local sides (BSTi0-31

and LSTi0-31) must be aligned to this frame pulse and the

accompanying input clock, C8i.

C8o

T11

C8o Output Clock (5V Tolerant Three-state Output). This

pin outputs an 8.192MHz clock generated within the device.

The clock falling edge or rising edge is aligned with the output

frame boundary presented on FP8o; this edge polarity

alignment is controlled by the COPOL bit of the Control

(BSTo0-31 and LSTo0-31) will be aligned to this clock and the

accompanying output frame pulse, FP8o.

FP8o

R10

Frame Pulse Output (5V Tolerant Three-state Output).

When the Frame Pulse Width bit (FPW) of the Control

pulse. When the FPW bit is HIGH, this pin outputs a

244ns-wide frame pulse. The frame pulse, running at 8kHz

rate, will have the same format (ST-BUS or GCI-Bus) as the

input frame pulse (FP8i). Output data on both the Backplane

and Local sides (BSTo0-31 and LSTo0-31) will be aligned to

this frame pulse and the accompanying output clock, C8o.

C16o

P10

C16o Output Clock (5V Tolerant Three-state Output). This

pin outputs a 16.384MHz clock generated within the device.

The clock falling edge or rising edge is aligned with the output

frame boundary presented on FP16o; this edge polarity

alignment is controlled by the COPOL bit of the Control

(BSTo0-31 and LSTo0-31) will be aligned to this clock and the

accompanying output frame pulse, FP16o.

Zarlink Semiconductor Inc.

1...7 8 91011 12 13...68

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与ZL50064相关器件

型号	品牌	描述	获取价格	数据表
ZL50064QCC	ZARLINK	16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), a	获取价格
ZL50070	ZARLINK	24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50070GA	MICROSEMI	Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484	获取价格
ZL50070GA	ZARLINK	Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484	获取价格
ZL50070GAC	ZARLINK	24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50070GAG2	ZARLINK	24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50073	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50073_06	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50073GA	ZARLINK	Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484	获取价格
ZL50073GAC	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50073GAG2	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50074	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格
ZL50074GAC	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格
ZL50074GAG2	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格
ZL50074GDC	MICROSEMI	Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484	获取价格
ZL50075	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Str	获取价格
ZL50075GAC	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Str	获取价格
ZL50075GAG2	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Str	获取价格
ZL50110	ZARLINK	128, 256 and 1024 Channel CESoP Processors	获取价格
ZL50110_06	ZARLINK	128, 256 and 1024 Channel CESoP Processors	获取价格

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