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ZL50070GAC PDF预览

ZL50070GAC

更新时间： 2024-01-23 20:21:04
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信集成电路电信转换电路电信电路
页数 文件大小 规格书
66页 616K
描述
24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs

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ZL50070GAC 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：BGA,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.8
Is Samacsys：NJESD-30 代码：S-PBGA-B484
JESD-609代码：e0长度：23 mm
湿度敏感等级：1功能数量：1
端子数量：484最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
认证状态：Not Qualified座面最大高度：2.16 mm
标称供电电压：1.8 V表面贴装：YES
电信集成电路类型：DIGITAL TIME SWITCH温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：23 mm
Base Number Matches：1

ZL50070GAC 数据手册

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ZL50070  
24 K Channel Digital Switch with High Jitter  
Tolerance, Rate Conversion per Group of  
4 Streams (8, 16, 32 or 64 Mbps),  
and 96 Inputs and 96 Outputs  
Data Sheet  
January 2006  
Features  
•
24,576 channel x 24,576 channel non-blocking  
Ordering Information  
digital Time Division Multiplex (TDM) switch at  
65.536 Mbps, 32.768 Mbps and 16.384 Mbps or  
using a combination of rates  
ZL50070GAC  
484 Ball PBGA  
Trays  
ZL50070GAG2 484 Ball PBGA** Trays  
**Pb Free Tin/Silver/Copper  
•
•
•
•
•
12,288 channel x 12,288 channel non-blocking  
digital TDM switch at 8.192 Mbps  
-40°C to +85°C  
High jitter tolerance with multiple input clock  
sources and frequencies  
•
Per-channel constant or variable throughput delay  
for frame integrity and low latency applications  
Up to 96 serial TDM input streams, divided into  
24 groups with 4 input streams per group  
Up to 96 serial TDM output streams, divided into  
24 groups with 4 output streams per group  
•
•
•
•
•
Per-stream Bit Error Rate (BER) test circuits  
Per-channel high impedance output control  
Per-channel force high output control  
Per-channel message mode  
Per-group input and output data rate conversion  
selection at 65.536 Mbps, 32.768 Mbps,  
16.384 Mbps and 8.192 Mbps. Input and output  
data group rates can differ  
Control interface compatible with Intel and  
Motorola Selectable 32 bit and 16 bit non-  
multiplexed buses  
•
Per-group input bit delay for flexible sampling  
point selection  
•
•
Connection Memory block programming  
Supports ST-BUS and GCI-Bus standards for  
input and output timing  
•
•
Per-group output fractional bit advancement  
Four sets of output timing signals for interfacing  
additional devices  
•
•
IEEE 1149.1 (JTAG) test port  
3.3 V I/O with 5 V tolerant inputs; 1.8 V core  
voltage  
•
Per-channel A-Law/µ-Law Translation  
VDD_CORE  
VDD_IO  
VSS  
ODE  
PWR  
STiA0  
STiB0  
STiC0  
SToA0  
SToB0  
Data Memory  
P/S  
Converter  
SToC0  
SToD0  
STiD0  
:
S/P  
Converter  
:
:
:
STiA23  
STiB23  
STiC23  
STiD23  
SToA23  
SToB23  
Connection Memory  
SToC23  
SToD23  
Input  
Timing  
Output  
Timing  
FPi2-0  
CKi2-0  
CK_SEL1-0  
FPo3-0  
Timing  
Test Access  
Port  
Microprocessor Interface  
and Control Registers  
CKo3-0  
Figure 1 - ZL50070 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.  
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