Datasheet > ZL50073_06

ZL50073_06

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		开关
页数	文件大小	规格书
68页	618K
描述
32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs

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ZL50073_06 数据手册

ZL50073

32 K Channel Digital Switch with High Jitter

Tolerance, Rate Conversion per Group of

4 Streams (8, 16, 32 or 64 Mbps),

and 128 Inputs and 128 Outputs

Data Sheet

January 2006

Features

•

32,768 channel x 32,768 channel non-blocking

Ordering Information

digital Time Division Multiplex (TDM) switch at

65.536 Mbps, 32.768 Mbps and 16.384 Mbps or

using a combination of rates

ZL50073GAC

484 Ball PBGA

Trays

ZL50073GAG2 484 Ball PBGA** Trays

**Pb Free Tin/Silver/Copper

•

16,384 channel x 16,384 channel non-blocking

digital TDM switch at 8.192 Mbps

-40°C to +85°C

High jitter tolerance with multiple input clock

sources and frequencies

•

Per-channel constant or variable throughput delay

for frame integrity and low latency applications

Up to 128 serial TDM input streams, divided into

32 groups with 4 input streams per group

Up to 128 serial TDM output streams, divided into

32 groups with 4 output streams per group

•

Per-stream Bit Error Rate (BER) test circuits

Per-channel high impedance output control

Per-channel force high output control

Per-channel message mode

Per-group input and output data rate conversion

selection at 65.536 Mbps, 32.768 Mbps,

16.384 Mbps and 8.192 Mbps. Input and output

data group rates can differ

Control interface compatible with Intel and

Motorola Selectable 32 bit and 16 bit non-

multiplexed buses

•

Per-group input bit delay for flexible sampling

point selection

•

Connection Memory block programming

Supports ST-BUS and GCI-Bus standards for

input and output timing

•

Per-group output fractional bit advancement

Four sets of output timing signals for interfacing

additional devices

•

IEEE 1149.1 (JTAG) test port

3.3 V I/O with 5 V tolerant inputs; 1.8 V core

voltage

•

Per-channel A-Law/µ-Law Translation

VDD_CORE

VDD_IO

VSS

ODE

PWR

STiA0

STiB0

STiC0

STiD0

SToA0

SToB0

Data Memory

P/S

SToC0

Converter

SToD0

S/P

Converter

STiA31

STiB31

STiC31

STiD31

SToA31

SToB31

Connection Memory

SToC31

SToD31

Input

Timing

Output

Timing

FPi2-0

CKi2-0

CK_SEL1-0

Timing

Test Access

Port

Microprocessor Interface

and Control Registers

FPo3-0

CKo3-0

Figure 1 - ZL50073 Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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ZL50073GA	ZARLINK	Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484	获取价格
ZL50073GAC	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50073GAG2	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
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ZL50074GAG2	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格