ZL50016
Data Sheet
1.0 Pinout Diagrams
1.1 BGA Pinout
1
2
3
4
5
NC
6
7
8
9
10
NC
FPi
11
12
13
14
15
16
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
16
A
B
A
B
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
D6
NC
NC
CKi
NC
NC
NC
NC
VDD_
COREA
STi10
STi9
STi11
STi14
STi15
STi5
VSS
STi4
STi7
STi3
VDD_IO
STi13
CKo2
STi6
STi2
VSS
STi0
STi1
NC
CKo0
CKo1
NC
IC_Open IC_Open IC_GND
ODE
C
D
C
D
VSS
NC
IC_Open IC_Open IC_Open IC_GND
FPo_
VSS
STio15
STio14
FPo2
VDD_IO
STi8
STi12
VSS
IC_GND STio13
VDD_IO
STio12
FPo3
OFF1
VDD_
CORE
VDD_
CORE
E
F
E
F
NC
NC
NC
VSS
VDD_IO
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
FPo_
OFF2
VDD_IO
TDo
NC
VSS
VSS
VSS
VSS
VSS
VSS
D10
D11
D14
D12
NC
VDD_IO IC_Open
G
H
G
H
RESET IC_GND IC_Open
VDD_
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
A12
A9
A13
A10
FPo1
FPo0
A11
FPo_
OFF0
VSS
VSS
VSS
A7
COREA
J
J
VDD_IOA VDD_IOA
VSS
VSS
CKo3
VDD_IO
A3
A4
A5
A8
A2
A6
VDD_
COREA
K
K
VSS
TMS
TRST
TDi
VSS
TCK
D0
VDD_IO IC_Open
A0
A1
VDD_
COREA
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
L
M
N
L
M
N
VDD_IO
VDD_IO
STio10
STio11
STio9
STio8
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
MOT
MODE_
4M0
NC
NC
NC
NC
NC
2
VSS
VSS
_INTEL
R/W
DTA_
RDY
VDD_IO
STio0 STOHZ3
D1
D5
D3
D4
NC
7
D7
D13
NC
D15
NC
10
STio4
VDD_IO STOHZ5
_WR
P
R
P
R
VSS
STio1
STio3 STOHZ1
D8
STio5 STOHZ4 STOHZ6
VSS
STio6
NC
STOHZ7
STio7
NC
MODE_
STOHZ0 STio2 STOHZ2
D2
NC
6
D9
CS
NC
11
DS_RD
NC
4M1
NC
T
T
NC
3
NC
4
NC
5
NC
8
9
12
13
14
15
Note: A1 corner identified by metallized marking.
Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50016 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
8
Zarlink Semiconductor Inc.