Z538001VSC

更新时间： 2024-02-15 02:56:16

品牌	Logo	应用领域
ZILOG		总线控制器微控制器和处理器计算机
页数	文件大小	规格书
37页	456K
描述
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

Z538001VSC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	QCCJ, LDCC44,.7SQ
针数：	44	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
地址总线宽度：	3	最大数据传输速率：	1.5 MBps
驱动器接口标准：	X3.131	外部数据总线宽度：	8
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
长度：	16.5862 mm	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	240
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Bus Controllers
最大压摆率：	15 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	16.5862 mm	uPs/uCs/外围集成电路类型：	BUS CONTROLLER, SCSI
Base Number Matches：	1

Z538001VSC 数据手册

ILOG

Z5380 SCSI

FUNCTIONAL DESCRIPTION (Continued)

This bit should also be set during DMA send operations.

Bit 1. Assert /ATN. /ATN may be asserted on the SCSI Bus

by setting this bit to a one (1) if the Target Mode bit (Mode

initiator to request a Message Out bus phase. Note that

sinceAssert/SELandAssert/ATNareinthesameregister,

a select with /ATN may be implemented with one CPU

write. /ATN may be deasserted by resetting this bit to zero.

A read of this register simply reflects the status of this bit.

Address: 1

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

Assert Data Bus

Assert /ATN

Assert /SEL

Assert /BSY

Bit 2. Assert /SEL. Writing a one (1) into this bit position

asserts /SEL onto the SCSI Bus. /SEL is normally asserted

after Arbitration has been successfully completed. /SEL

may be disabled by resetting bit 2 to a zero. A read of this

Assert /ACK

Lost Arbitration

Arbitration in Progress

Assert /RST

Bit 3. Assert /BSY. Writing a one (1) into this bit position

asserts /BSY onto the SCSI Bus. Conversely, a zero resets

the /BSY signal. Asserting /BSY indicates a successful

selection or reselection. Resetting this bit creates a Bus-

Disconnect condition. Reading this register reflects bit

status.

Figure 6. Initiator Command Register

Address: 1

(Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Bit4.Assert/ACK. Bit4isusedbythebusinitiatortoassert

/ACK on the SCSI Bus. In order to assert /ACK, the Target

Mode bit (Mode Register, bit 6) must be False. Writing a

zero to this bit deasserts /ACK. Reading this register

reflects bit status.

Assert Data Bus

Assert /ATN

Assert /SEL

Assert /BSY

Assert /ACK

"0"

Bit 5. “0” (Write Bit). Bit 5 should be written with a zero for

proper operation.

Test Mode

Assert /RST

Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active,

indicates that the SCSI detected a Bus-Free condition,

arbitrated for use of the bus by asserting /BSY and its ID on

the Data Bus, and lost Arbitration due to /SEL being

asserted by another bus device. This bit is active only

when the Arbitrate bit (Mode Register, bit 0) is active.

Figure 7. Initiator Command Register

The following describes the operation of all bits in the

Initiator Command Register:

Bit 6. Test Mode (Write Bit). Bit 6 is written during a test

environment to disable all output drivers, effectively re-

movingtheZ5380fromthecircuit.Resettingthisbitreturns

the part to normal operation.

Bit 0. Assert Data Bus. This bit, when set, allows the

contentsoftheOutputDataRegistertobeenabledaschip

outputs on the signals /DB7-DB0. Parity is also generated

and asserted on /DBP.

Bit 6. AIP (Arbitration in Process - Read Bit). Bit 6 is used

to determine if Arbitration is in progress. For this bit to be

active, the Arbitrate bit (Mode Register, bit 0) must have

been set previously. It indicates that a Bus-Free condition

has been detected and that the chip has asserted /BSY

and put the contents of the Output Data Register onto the

SCSI Bus. AIP will remain active until the Arbitrate bit is

reset.

When connected as an Initiator, the outputs are only

enabled if the Target Mode bit (Mode Register, bit 6) is 0,

the received signal I//O is False, and the phase signals (C/

/D, I//O, and /MSG) match the contents of the Assert C//D,

Assert I//O, and Assert /MSG in the Target Command

Bit 7. Assert /RST. Whenever a one is written to bit 7 of the

Initiator Command Register, the /RST signal is asserted on

PS97SCC0100

PS009101-0201

1...3 4 567 8 9...37

中文翻译

下载PDF

与Z538001VSC相关器件

型号	品牌	获取价格	描述	数据表
Z5380P	ETC	获取价格	Interface IC
Z5380PSC	ZILOG	获取价格	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40
Z5380PSCXXXX	ZILOG	获取价格	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40
Z5380V	ETC	获取价格	Interface IC
Z5380VSC	ZILOG	获取价格	SCSI Bus Controller, CMOS, PQCC44, PLASTIC, LCC-44
Z5380VSCXXXX	ZILOG	获取价格	暂无描述
Z53C80	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z53C8003PSC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z53C8003PSG	ZILOG	获取价格	IC SCSI BUS CONTROLLER, PDIP48, PLASTIC, DIP-48, Bus Controller
Z53C8003VSC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)

与Z538001VSC相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

2
电感耐压值及其与电感大小的关系
2024-06-07

5
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

4
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

3

产品中心

服务支持

精选活动

关于我们

帮助中心

Z538001VSC

Z538001VSC 技术参数

Z538001VSC 数据手册

与Z538001VSC相关器件

与Z538001VSC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

Z538001VSC

Z538001VSC 技术参数

Z538001VSC 数据手册

与Z538001VSC相关器件

与Z538001VSC相关文章

您还可以找

您在本页遇到什么问题？