Z538001VSC

更新时间： 2024-02-16 14:40:32

品牌	Logo	应用领域
ZILOG		总线控制器微控制器和处理器计算机
页数	文件大小	规格书
37页	456K
描述
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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技术参数
数据手册

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Z538001VSC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	QCCJ, LDCC44,.7SQ
针数：	44	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
地址总线宽度：	3	最大数据传输速率：	1.5 MBps
驱动器接口标准：	X3.131	外部数据总线宽度：	8
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
长度：	16.5862 mm	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	240
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Bus Controllers
最大压摆率：	15 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	16.5862 mm	uPs/uCs/外围集成电路类型：	BUS CONTROLLER, SCSI
Base Number Matches：	1

Z538001VSC 数据手册

ILOG

Z5380 SCSI

Table 1. Register Summary

Address

Address: 0

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

A2 A1 A0 R/W

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

R/W

Current SCSI Data

Output Data

Initiator Command

Mode

R/W

Target Command

Current SCSI Bus Status

Select Enable

Bus and Status

Start DMA Send

Input Data

Start DMA Target Receive

Reset Parity/Interrupt

Start DMA Initiator Receive

Figure 4. Current SCSI Data Register

Address: 0

(Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Data Registers

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

The data registers are used to transfer SCSI commands,

data, status, and message bytes between the micropro-

cessor Data Bus and the SCSI Bus. The Z5380 does not

interpret any information that passes through the data

registers. The data registers consist of the transparent

CurrentSCSIDataRegister, theOutputDataRegister, and

the Input Data Register.

Current SCSI Data Register. Address 0 (Read Only). The

Current SCSI Data Register (Figure 4) is a read-only

registerwhichallowsthemicroprocessortoreadtheactive

SCSI Data Bus. This is accomplished by activating /CS

withanaddressonA2-A0of000andissuingan/IORpulse.

If parity checking is enabled, the SCSI Bus parity is

checked at the beginning of the read cycle. This register

is used during a programmed I/O data read or during

Arbitration to check for higher priority arbitrating devices.

Parity is not guaranteed valid during Arbitration.

Figure 5. Output Data Register

Initiator Command Register. Address 1 (Read/Write).

The Initiator Command Register (Figures 6 and 7) are read

and write registers which assert certain SCSI Bus signals,

monitors those signals, and monitors the progress of bus

arbitration. Many of these bits are significant only when

being used as an Initiator; however, most can be used

during Target role operation.

OutputDataRegister.Address0(WriteOnly).TheOutput

Data Register (Figure 5) is a write-only register that is used

to send data to the SCSI Bus. This is accomplished by

either using a normal CPU write, or under DMA control, by

using /IOW and /DACK. This register also asserts the

proper ID bits on the SCSI Bus during the Arbitration and

Selection phases.

PS97SCC0100

PS009101-0201

1 2 3 456 7 8...37

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与Z538001VSC相关器件

型号	品牌	描述	获取价格	数据表
Z5380P	ETC	Interface IC	获取价格
Z5380PSC	ZILOG	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40	获取价格
Z5380PSCXXXX	ZILOG	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40	获取价格
Z5380V	ETC	Interface IC	获取价格
Z5380VSC	ZILOG	SCSI Bus Controller, CMOS, PQCC44, PLASTIC, LCC-44	获取价格
Z5380VSCXXXX	ZILOG	暂无描述	获取价格

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