Contents
1
Introduction...................................................................................................... 7
1.1
1.2
1.3
1.4
Abstract................................................................................................. 7
Major Features ....................................................................................... 7
Terminology........................................................................................... 9
References............................................................................................11
2
Low Power Features..........................................................................................13
2.1
Clock Control and Low-Power States ........................................................13
2.1.1 Package/Core Low-Power State Descriptions................................15
2.2
2.3
2.4
2.5
Dynamic Cache Sizing ............................................................................22
Enhanced Intel SpeedStep® Technology...................................................23
Enhanced Low-Power States....................................................................24
FSB Low Power Enhancements.................................................................25
2.5.1
CMOS Front Side Bus ................................................................25
2.6
Intel® Burst Performance Technology (Intel® BPT) ..................................26
3
Electrical Specifications .....................................................................................27
3.1
3.2
3.3
FSB, GTLREF, and CMREF........................................................................27
Power and Ground Pins...........................................................................27
Decoupling Guidelines ............................................................................28
3.3.1
3.3.2
VCC Decoupling .........................................................................28
FSB AGTL+ Decoupling..............................................................28
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
FSB Clock (BCLK[1:0]) and Processor Clocking..........................................28
Voltage Identification and Power Sequencing.............................................28
Catastrophic Thermal Protection ..............................................................31
Reserved and Unused Pins ......................................................................31
FSB Frequency Select Signals (BSEL[2:0])................................................31
FSB Signal Groups .................................................................................31
CMOS Asynchronous Signals ...................................................................33
Maximum Ratings ..................................................................................33
Processor DC Specifications.....................................................................34
AGTL+ FSB Specifications .......................................................................45
4
5
Package Mechanical Specifications and Pin Information..........................................47
4.1
Package Mechanical Specifications ...........................................................47
4.1.1 Processor Package Weight .........................................................47
4.2
4.3
Processor Pinout Assignment...................................................................49
Signal Description..................................................................................56
Thermal Specifications and Design Considerations ................................................65
5.1 Thermal Specifications............................................................................68
5.1.1
5.1.2
5.1.3
Thermal Diode .........................................................................68
Intel® Thermal Monitor.............................................................70
Digital Thermal Sensor..............................................................72
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