XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
SEPTEMBER 2007
REV. 1.0.2
FEATURES
GENERAL DESCRIPTION
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Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and Philip’s SC16C654B
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The XR16V654 (V654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, programmable transmit and receive FIFO
trigger levels, automatic hardware and software flow
control, and data rates of up to 16 Mbps at 4X
sampling rate. Each UART has a set of registers that
provide the user with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The V654 is available in a 48-
pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP
and 100-pin QFP packages. The 64-pin and 80-pin
packages only offer the 16 mode interface, but the
48, 68 and 100 pin packages offer an additional 68
mode interface which allows easy integration with
Motorola processors. The XR16V654IV (64-pin)
offers three state interrupt output while the
XR16V654DIV provides continuous interrupt output.
The 100 pin package provides additional FIFO status
outputs (TXRDY# and RXRDY# A-D), separate
infrared transmit data outputs (IRTX A-D) and
channel C external clock input (CHCCLK). The
XR16V654 is compatible with the industry standard
ST16C554 and ST16C654/654D.
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Intel or Motorola Data Bus Interface select
Four independent UART channels
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Register Set Compatible to 16C550
Data rates of up to 16 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
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2.25V to 3.6V supply operation
Sleep Mode with automatic wake-up
Crystal oscillator or external clock input
APPLICATIONS
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Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
NOTE: 1 Covered by U.S. Patent #5,649,122.
Cellular Data Devices
Factory Automation and Process Controls
F
IGURE 1. XR16V654 BLOCK DIAGRAM
2.25V to 3.6V VCC
GND
* 5 Volt Tolerant Inputs
(Except XTAL1 input)
A2:A0
D7:D0
UART Channel A
64 Byte TX FIFO
IOR#
IOW#
CSA#
CSB#
UART
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
Regs
IR
ENDEC
TX & RX
BRG
64 Byte RX FIFO
CSC#
CSD#
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
UART Channel B
(same as Channel A)
INTA
INTB
INTC
Data Bus
Interface
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
UART Channel C
(same as Channel A)
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
UART Channel D
(same as Channel A)
Reset
16/68#
INTSEL
XTAL1
Crystal Osc/Buffer
CLKSEL
XTAL2
654 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com