Datasheet > XR16M781IL24-F

XR16M781IL24-F

更新时间： 2024-11-22 20:08:11

品牌	Logo	应用领域
艾科嘉 - EXAR		外围集成电路
页数	文件大小	规格书
52页	507K
描述
Serial I/O Controller, CMOS, PQCC24,

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技术参数
数据手册
替代型号

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XR16M781IL24-F 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	5.79	JESD-30 代码：	S-PQCC-N24
JESD-609代码：	e3	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	1.8/3.3 V
认证状态：	Not Qualified	子类别：	Serial IO/Communication Controllers
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：	1

XR16M781IL24-F 数据手册

XR16M781

1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE

AUGUST 2009

REV. 1.0.1

FEATURES

GENERAL DESCRIPTION

• VLIO bus interface

The XR16M781 (M781) is an enhanced Universal

Asynchronous Receiver and Transmitter (UART) with

a VLIO bus interface and has 64 bytes of transmit

and receive FIFOs, programmable transmit and

receive FIFO trigger levels, automatic hardware and

software flow control, and data rates of up to 20 Mbps

at 3.3V, 16 Mbps at 2.5V and 10 Mbps at 1.8V with

4X data sampling rate.

• Pin-to-pin compatible with SC16C850V and

SC16C850SV in 32-QFN package

• 20 Mbps maximum data rate

• Programmable TX/RX FIFO Trigger Levels

• TX/RX FIFO Level Counters

• Independent TX/RX Baud Rate Generator

• Fractional Baud Rate Generator

• Auto RTS/CTS Hardware Flow Control

• Auto XON/XOFF Software Flow Control

• Auto RS-485 Half-Duplex Direction Control

• Multidrop mode w/ Auto Address Detect

• Sleep Mode with Automatic Wake-up

• PowerSave mode

The Auto RS-485 Half-Duplex Direction control

feature simplifies both the hardware and software for

half-duplex RS-485 applications. In addition, the

Multidrop mode with Auto Address detection

increases the performance by simplifying the

software routines.

The Independent TX/RX Baud Rate Generator

feature allows the transmitter and receiver to operate

at different baud rates. Power consumption of the

M781 can be minmized by enabling the sleep mode

and PowerSave mode.

• Infrared (IrDA 1.0 and 1.1) mode

• 1.62V to 3.63V supply operation

• Crystal oscillator or external clock input

APPLICATIONS

The M781 has a 16550 compatible register set that

provide users with operating status and control,

receiver error indications, and modem serial interface

controls. An internal loopback capability allows

onboard diagnostics. The M781 is available in 24-pin

QFN, 32-pin QFN and 25-pin BGA packages.

• Personal Digital Assistants (PDA)

• Cellular Phones/Data Devices

• Battery-Operated Devices

NOTE: 1 Covered by U.S. Patent #5,649,122.

• Global Positioning System (GPS)

• Bluetooth

FIGURE 1. XR16M781 BLOCK DIAGRAM

VCC

(1.62 to 3.63 V)

PwrSave

LLA#

GND

AD7:AD0

IOR#

64 Byte TX FIFO

BRG

UART

Regs

TX, RX,

IOW#

CS#

RTS#, CTS#,

DTR#, DSR#,

RI#, CD#

TX &

ENDEC

INT

VLIO Bus

Interface

BRG

64 Byte RX FIFO

RESET#

XTAL1

XTAL2

Crystal Osc/Buffer

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...52

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XR16M781IL24-F 替代型号

型号	品牌	替代类型	描述	数据表
XR16M681IL24-F	EXAR	完全替代	Serial I/O Controller, CMOS, PQCC24

与XR16M781IL24-F相关器件

型号	品牌	获取价格	描述	数据表
XR16M781IL32	EXAR	获取价格	1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
XR16M781IL32-F	EXAR	获取价格	Serial I/O Controller, CMOS, PQCC32,
XR16M890	EXAR	获取价格	Single-Channel UARTs with Selectable Bus Interfaces
XR16M890_11	EXAR	获取价格	UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
XR16M890IL32	EXAR	获取价格	UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
XR16M890IL32-0C	EXAR	获取价格	UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
XR16M890IL32-F	EXAR	获取价格	Single-Channel UARTs with Selectable Bus Interfaces
XR16M890IL32TR	EXAR	获取价格	UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
XR16M890IL32TR-F	EXAR	获取价格	UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
XR16M890IL40	EXAR	获取价格	UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

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