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XQVR600-4CB228Q PDF预览

XQVR600-4CB228Q

更新时间： 2024-09-17 21:16:15
品牌 Logo 应用领域
赛灵思 - XILINX 栅可编程逻辑
页数 文件大小 规格书
14页 169K
描述
Field Programmable Gate Array, 3456 CLBs, 661111 Gates, 15552-Cell, CMOS, CQFP228, CERAMIC, QFP-228

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XQVR600-4CB228Q 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：CERAMIC, QFP-228针数：228
Reach Compliance Code：compliantECCN代码：USML XV(E)
HTS代码：8542.39.00.01风险等级：5.25
JESD-30 代码：S-CQFP-F228JESD-609代码：e0
长度：39.37 mm可配置逻辑块数量：3456
等效关口数量：661111输入次数：316
逻辑单元数量：15552输出次数：316
端子数量：228最高工作温度：125 °C
最低工作温度：-55 °C组织：3456 CLBS, 661111 GATES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：GQFF
封装等效代码：TPAK228,2.5SQ,25封装形状：SQUARE
封装形式：FLATPACK, GUARD RING峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.2/3.6,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class Q
座面最大高度：3.302 mm子类别：Field Programmable Gate Arrays
最大供电电压：2.625 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：100k Rad(Si) V
宽度：39.37 mmBase Number Matches：1

XQVR600-4CB228Q 数据手册

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0
R
QPro Virtex 2.5V Radiation  
Hardened FPGAs  
0
2
DS028 (v1.2) November 5, 2001  
Preliminary Product Specification  
-
Complete support for Unified Libraries, Relationally  
Placed Macros, and Design Manager  
Features  
•
•
•
0.22 µm 5-layer epitaxial process  
-
Wide selection of PC and workstation platforms  
QML certified  
•
•
SRAM-based in-system configuration  
Radiation hardened FPGAs for space and satellite  
applications  
-
-
Unlimited reprogrammability  
Four programming modes  
•
•
•
Guaranteed total ionizing dose to 100K Rad(si)  
Available to Standard Microcircuit Drawings. Contact  
Defense Supply Center Columbus (DSCC) for more  
information at http://www.dscc.dla.mil  
2
Latch-up immune to LET = 125 MeV cm /mg  
SEU immunity achievable with recommended  
redundancy implementation  
-
-
-
5962-99572 for XQVR300  
5962-99573 for XQVR600  
5962-99574 for XQVR1000  
•
•
Guaranteed over the full military temperature range  
(–55°C to +125°C)  
Fast, high-density Field-Programmable Gate Arrays  
-
-
-
Densities from 100k to 1M system gates  
System performance up to 200 MHz  
Hot-swappable for Compact PCI  
Description  
The QPro™ Virtex™ FPGA family delivers high-perfor-  
mance, high-capacity programmable logic solutions. Dra-  
matic increases in silicon efficiency result from optimizing  
the new architecture for place-and-route efficiency and  
exploiting an aggressive 5-layer-metal 0.22 µm CMOS pro-  
cess. These advances make QPro Virtex FPGAs powerful  
and flexible alternatives to mask-programmed gate arrays.  
The Virtex radiation hardened family comprises the three  
members shown in Table 1.  
•
•
Multi-standard SelectI/O™ interfaces  
-
-
16 high-performance interface standards  
Connects directly to ZBTRAM devices  
Built-in clock-management circuitry  
-
Four dedicated delay-locked loops (DLLs) for  
advanced clock control  
-
Four primary low-skew global clock distribution  
nets, plus 24 secondary global nets  
Building on experience gained from previous generations of  
FPGAs, the Virtex family represents a revolutionary step  
forward in programmable logic design. Combining a wide  
variety of programmable system features, a rich hierarchy of  
fast, flexible interconnect resources, and advanced process  
technology, the QPro Virtex family delivers a high-speed  
and high-capacity programmable logic solution that  
enhances design flexibility while reducing time-to-market.  
•
•
Hierarchical memory system  
-
-
-
LUTs configurable as 16-bit RAM, 32-bit RAM,  
16-bit dual-ported RAM, or 16-bit Shift Register  
Configurable synchronous dual-ported 4k-bit  
RAMs  
Fast interfaces to external high-performance RAMs  
Refer to the “Virtex™ 2.5V Field Programmable Gate  
Arrays” commercial data sheet for more information on  
device architecture and timing specifications.  
Flexible architecture that balances speed and density  
-
-
-
-
Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
-
-
-
Internal 3-state bussing  
IEEE 1149.1 boundary-scan logic  
Die-temperature sensing device  
•
Supported by FPGA Foundation™ and Alliance  
Development Systems  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS028 (v1.2) November 5, 2001  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234567...14

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