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QPro Virtex-II 1.5V Platform FPGAs
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DS122 (v2.0) December 21, 2007
Product Specification
Summary of QPro™ Virtex™-II Features
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Industry’s first military-grade platform FPGA solution
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High-performance clock management circuitry
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Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
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Up to 12 DCM (Digital Clock Manager) modules
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Precise clock de-skew
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100% factory tested
Flexible frequency synthesis
High-resolution phase shifting
Guaranteed over the full military temperature range
(–55°C to +125°C) or industrial temperature range
(–40°C to +100°C)
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16 global clock multiplexer buffers
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Active interconnect technology
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Ceramic and plastic wire-bond and flip-chip grid array
packages
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Fourth-generation segmented routing structure
Predictable, fast routing delay, independent of fanout
IP-immersion architecture
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Densities from 1M to 6M system gates
300+ MHz internal clock speed (Advance Data)
622+ Mb/s I/O (Advance Data)
SelectIO™-Ultra Technology
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Up to 824 user I/Os
19 single-ended and six differential standards
Programmable sink current (2 mA to 24 mA) per I/O
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SelectRAM™ Memory Hierarchy
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2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
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Up to 1 Mb of distributed SelectRAM resources
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PCI compliant (32/33 MHz) at 3.3V
Differential signaling
High-performance interfaces to external memory
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DRAM interfaces
622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
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SDR/DDR SDRAM
Network FCRAM
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Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
Reduced Latency DRAM
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SRAM interfaces
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Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
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SDR/DDR SRAM
QDR SRAM
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Built-in DDR input and output registers
CAM interfaces
Proprietary high-performance SelectLink
Technology
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Arithmetic functions
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Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
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High-bandwidth data path
Double Data Rate (DDR) link
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Flexible logic resources
Web-based HDL generation methodology
Up to 67,584 internal registers/latches with Clock Enable
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Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
Up to 67,584 look-up tables (LUTs) or cascadable 16-
bit shift registers
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Integrated VHDL and Verilog design flows
Compilation of 10M system gates designs
Internet Team Design (ITD) tool
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Wide multiplexers and wide-input function support
Horizontal cascade chain and sum-of-products support
Internal 3-state busing
© 2003, 2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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