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XPC755BRX300LE PDF预览

XPC755BRX300LE

更新时间: 2024-01-04 01:30:34
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
56页 1521K
描述
32-BIT, 300MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360

XPC755BRX300LE 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360针数:360
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.31.00.01风险等级:5.16
其他特性:ALSO REQUIRES 2.5V OR 3.3V SUPPLY地址总线宽度:32
位大小:32边界扫描:YES
最大时钟频率:100 MHz外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-CBGA-B360长度:25 mm
低功率模式:YES端子数量:360
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:BGA
封装等效代码:BGA360,19X19,50封装形状:SQUARE
封装形式:GRID ARRAY电源:2,2.5/3.3 V
认证状态:Not Qualified座面最大高度:3.2 mm
速度:300 MHz子类别:Microprocessors
最大供电电压:2.1 V最小供电电压:1.8 V
标称供电电压:2 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:25 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

XPC755BRX300LE 数据手册

 浏览型号XPC755BRX300LE的Datasheet PDF文件第2页浏览型号XPC755BRX300LE的Datasheet PDF文件第3页浏览型号XPC755BRX300LE的Datasheet PDF文件第4页浏览型号XPC755BRX300LE的Datasheet PDF文件第5页浏览型号XPC755BRX300LE的Datasheet PDF文件第6页浏览型号XPC755BRX300LE的Datasheet PDF文件第7页 
Document Number: MPC755EC  
Rev. 8, 02/2006  
Freescale Semiconductor  
Technical Data  
MPC755  
RISC Microprocessor  
Hardware Specifications  
Contents  
This document is primarily concerned with the MPC755;  
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
4. Electrical and Thermal Characteristics . . . . . . . . . . . . 6  
5. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
6. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
7. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 32  
8. System Design Information . . . . . . . . . . . . . . . . . . . 36  
9. Document Revision History . . . . . . . . . . . . . . . . . . . 50  
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 53  
however, unless otherwise noted, all information here also  
applies to the MPC745. The MPC755 and MPC745 are  
reduced instruction set computing (RISC) microprocessors  
that implement the PowerPC™ instruction set architecture.  
This document describes pertinent physical characteristics of  
the MPC755. For information on specific MPC755 part  
numbers covered by this or other specifications, see  
Section 10, “Ordering Information.” For functional  
characteristics of the processor, refer to the MPC750 RISC  
Microprocessor Family Users Manual.  
To locate any published errata or updates for this document,  
refer to the website listed on the back cover of this document.  
1 Overview  
The MPC755 is targeted for low-cost, low-power systems  
and supports the following power management  
features—doze, nap, sleep, and dynamic power  
management. The MPC755 consists of a processor core and  
an internal L2 tag combined with a dedicated L2 cache  
interface and a 60x bus. The MPC745 is identical to the  
MPC755 except it does not support the L2 cache interface.  
Figure 1 shows a block diagram of the MPC755.  
© Freescale Semiconductor, Inc., 2006. All rights reserved.  

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