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XPC755BPX300LD PDF预览

XPC755BPX300LD

更新时间: 2024-09-22 20:58:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
76页 1751K
描述
32-BIT, 300MHz, RISC PROCESSOR, PBGA360, 25 X 25 MM, 2.77 MM HEIGHT, 1.27 MM PITCH, PLASTIC, FCBGA-360

XPC755BPX300LD 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:360
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.16
Is Samacsys:N地址总线宽度:32
位大小:32边界扫描:YES
最大时钟频率:100 MHz外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-PBGA-B360JESD-609代码:e0
长度:25 mm低功率模式:YES
端子数量:360封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:2.77 mm速度:300 MHz
最大供电电压:2.1 V最小供电电压:1.9 V
标称供电电压:2 V表面贴装:YES
技术:CMOS端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:25 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

XPC755BPX300LD 数据手册

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Advance Information  
MPC755EC/D  
Rev. 6, 9/2002  
MPC755  
RISC Microprocessor  
Hardware Specifications  
This document is primarily concerned with the MPC755; however, unless otherwise noted, all  
information here also applies to the MPC745. The MPC755 and MPC745 are reduced  
instruction set computing (RISC) microprocessors that implement the PowerPC instruction  
set architecture. This document describes pertinent physical characteristics of the MPC755.  
For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor  
Family Users Manual.  
This document contains the following topics:  
Topic  
Page  
1
Section 1.1, “Overview”  
Section 1.2, “Features”  
3
Section 1.3, “General Parameters”  
Section 1.4, “Electrical and Thermal Characteristics”  
Section 1.5, “Pin Assignments”  
Section 1.6, “Pinout Listings”  
Section 1.7, “Package Description”  
Section 1.8, “System Design Information”  
Section 1.9, “Document Revision History”  
Section 1.10, “Ordering Information”  
5
6
23  
25  
30  
34  
47  
49  
To locate any published errata or updates for this document, refer to the website at  
http://www.motorola.com/semiconductors.  
1.1 Overview  
The MPC755 is targeted for low-cost, low-power systems and supports the following power  
management features—doze, nap, sleep, and dynamic power management. The MPC755  
consists of a processor core and an internal L2 tag combined with a dedicated L2 cache  
interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support  
the L2 cache interface.  
Figure 1 shows a block diagram of the MPC755.  

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