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XPC107APX100LC PDF预览

XPC107APX100LC

更新时间： 2024-11-29 19:54:51
品牌 Logo 应用领域
恩智浦 - NXP 时钟PC
页数 文件大小 规格书
49页 466K
描述
IC,PERIPHERAL (MULTIFUNCTION) CONTROLLER,CMOS,BGA,503PIN

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XPC107APX100LC 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：BGA包装说明：33 X 33 MM, 2.75 HEIGHT, 1.27 MM PITCH, PLASTIC, FC-PBGA-503
针数：503Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.85
边界扫描：YES总线兼容性：PCI
最大时钟频率：66 MHzJESD-30 代码：S-PBGA-B503
JESD-609代码：e0长度：33 mm
端子数量：503封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA503,25X25,50
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5,2.5/3.3,3.3 V
认证状态：Not QualifiedRAM（字数）：256
座面最大高度：2.75 mm子类别：Other Microprocessor ICs
最大供电电压：2.625 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：33 mmBase Number Matches：1

XPC107APX100LC 数据手册

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Advance Information  
MPC107EC/D  
Rev. 1, 11/2002  
MPC107  
PCI Bridge/Memory  
Controller  
Hardware Specifications  
This document provides an overview of the MPC107 PCI bridge/memory controller  
(PCIB/MC) for high-performance embedded systems. The MPC107 is a cost-effective,  
general-purpose PCIB/MC for applications using PCI in networking infrastructure,  
telecommunications, and other embedded markets. It can be used in applications such as  
network routers and switches, mass storage subsystems, network appliances, and print and  
imaging systems.  
This document describes pertinent electrical and physical characteristics of the MPC107. For  
functional characteristics of the processor, refer to the MPC107 PCI Bridge/Memory  
Controller User’s Manual (MPC107UM/D).  
This document contains the following topics:  
Topic  
Page  
1
Section 1.1, “Overview”  
Section 1.2, “Features”  
2
Section 1.3, “General Parameters”  
Section 1.4, “Electrical and Thermal Characteristics”  
Section 1.5, “Package Description”  
Section 1.6, “PLL Configuration”  
Section 1.7, “System Design Information”  
Section 1.8, “Document Revision History”  
Section 1.9, “Ordering Information”  
4
4
28  
36  
36  
44  
46  
To locate any published errata or updates for this document, refer to the web site at  
http://www.motorola.com/semiconductors.  
1.1 Overview  
The MPC107 integrates a PCI bridge, memory controller, DMA controller, PIC timers, a  
message unit with an Intelligent Input/Output (I O) message controller, and an  
2
2
Inter-Integrated Circuit (I C) controller. The integration reduces the overall packaging  
requirements and the number of discrete devices required for an embedded system.  
Figure 1 shows the major functional units within the MPC107. Note that this is a conceptual  
block diagram intended to show basic features rather than an attempt to show how these  
features are physically implemented.  
 
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