XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
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Contents
1
2
Features............................................................................................................................ 11
Introduction....................................................................................................................... 12
2.1
2.2
2.3
2.4
2.5
2.6
Description .................................................................................................................. 12
Related Documents ........................................................................................................ 12
Document Conventions.................................................................................................... 13
Ordering Information ...................................................................................................... 13
Terminal Assignments ..................................................................................................... 14
Terminal Descriptions...................................................................................................... 17
3
Description........................................................................................................................ 22
3.1
Power-Up/Power-Down Sequencing..................................................................................... 22
3.1.1
Power-Up Sequence ............................................................................................ 22
Power-Down Sequence......................................................................................... 23
3.1.2
3.2
Express Interface........................................................................................................... 23
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
External Reference Clock ...................................................................................... 23
Clock Generator ................................................................................................. 23
Beacon............................................................................................................ 24
WAKE ............................................................................................................ 24
Initial Flow Control Credits ..................................................................................... 24
PCI Express Message Transactions.......................................................................... 24
3.3
3.4
GPIO Terminals ............................................................................................................ 25
Serial EEPROM ............................................................................................................ 25
3.4.1
3.4.2
3.4.3
3.4.4
Serial Bus Interface Implementation .......................................................................... 26
Serial Bus Interface Protocol................................................................................... 26
Serial Bus EEPROM Application .............................................................................. 28
Accessing Serial Bus Devices Through Software........................................................... 31
3.5
Switch Reset Features..................................................................................................... 31
4
XIO3130 Configuration Register Space ................................................................................. 33
4.1
PCI Configuration Register Space Overview ........................................................................... 33
PCI Express Upstream Port Registers .................................................................................. 34
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
PCI Configuration Space (Upstream Port) Register Map .................................................. 35
Vendor ID Register.............................................................................................. 36
Device ID Register .............................................................................................. 36
Command Registers ............................................................................................ 36
Status Register .................................................................................................. 37
Class Code and Revision ID Register ........................................................................ 39
Cache Line Size Register ...................................................................................... 39
Primary Latency Timer Register............................................................................... 39
Header Type Register .......................................................................................... 40
4.2.10 BIST Register .................................................................................................... 40
4.2.11 Primary Bus Number............................................................................................ 40
4.2.12 Secondary Bus Number ........................................................................................ 40
4.2.13 Subordinate Bus Number....................................................................................... 41
4.2.14 Secondary Latency Timer Register ........................................................................... 41
4.2.15 I/O Base Register................................................................................................ 41
4.2.16 I/O Limit Register ................................................................................................ 42
4.2.17 Secondary Status Register..................................................................................... 42
4.2.18 Memory Base Register ......................................................................................... 43
4.2.19 Memory Limit Register.......................................................................................... 43
4.2.20 Pre-fetchable Memory Base Register......................................................................... 43
4.2.21 Pre-Fetchable Memory Limit Register ........................................................................ 44
2
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