XIO3130
www.ti.com
SLLS693C–MAY 2007–REVISED JUNE 2008
4.2.22 Pre-Fetchable Base Upper 32 Bits Register................................................................. 44
4.2.23 Pre-fetchable Limit Upper 32 Bits Register .................................................................. 45
4.2.24 I/O Base Upper 16 Bits Register .............................................................................. 45
4.2.25 I/O Limit Upper 16 Bits Register............................................................................... 45
4.2.26 Capabilities Pointer Register................................................................................... 45
4.2.27 Interrupt Line Register .......................................................................................... 46
4.2.28 Interrupt Pin Register ........................................................................................... 46
4.2.29 Bridge Control Register......................................................................................... 46
4.2.30 Capability ID Register........................................................................................... 48
4.2.31 Next-Item Pointer Register ..................................................................................... 48
4.2.32 Power Management Capabilities Register ................................................................... 48
4.2.33 Power Management Control/Status Register ................................................................ 49
4.2.34 Power Management Bridge Support Extension Register .................................................. 50
4.2.35 Power Management Data Register ........................................................................... 50
4.2.36 MSI Capability ID Register ..................................................................................... 50
4.2.37 Next-Item Pointer Register ..................................................................................... 50
4.2.38 MSI Message Control Register ................................................................................ 51
4.2.39 MSI Message Address Register............................................................................... 51
4.2.40 MSI Message Upper Address Register....................................................................... 52
4.2.41 MSI Message Data Register ................................................................................... 52
4.2.42 Capability ID Register........................................................................................... 52
4.2.43 Next-Item Pointer Register ..................................................................................... 52
4.2.44 Subsystem Vendor ID Register................................................................................ 53
4.2.45 Subsystem ID Register ......................................................................................... 53
4.2.46 PCI Express Capability ID Register........................................................................... 53
4.2.47 Next-Item Pointer Register ..................................................................................... 54
4.2.48 PCI Express Capabilities Register ............................................................................ 54
4.2.49 Device Capabilities Register ................................................................................... 54
4.2.50 Device Control Register ........................................................................................ 55
4.2.51 Device Status Register ......................................................................................... 56
4.2.52 Link Capabilities Register ...................................................................................... 57
4.2.53 Link Control Register............................................................................................ 58
4.2.54 Link Status Register............................................................................................. 59
4.2.55 Serial Bus Data Register ....................................................................................... 59
4.2.56 Serial Bus Index Register ...................................................................................... 59
4.2.57 Serial Bus Slave Address Register............................................................................ 60
4.2.58 Serial Bus Control and Status Register ...................................................................... 60
4.2.59 Upstream Port Link PM Latency Register.................................................................... 61
4.2.60 Global Chip Control Register .................................................................................. 63
4.2.61 GPIO A Control Register ....................................................................................... 64
4.2.62 GPIO B Control Register ....................................................................................... 66
4.2.63 GPIO C Control Register ....................................................................................... 68
4.2.64 GPIO D Control Register ....................................................................................... 70
4.2.65 GPIO Data Register............................................................................................. 72
4.2.66 TI Proprietary Register.......................................................................................... 75
4.2.67 TI Proprietary Register.......................................................................................... 75
4.2.68 TI Proprietary Register.......................................................................................... 75
4.2.69 TI Proprietary Register.......................................................................................... 76
4.2.70 TI Proprietary Register.......................................................................................... 76
4.2.71 TI Proprietary Register.......................................................................................... 76
4.2.72 Subsystem Access Register ................................................................................... 77
4.2.73 General Control Register ....................................................................................... 77
4.2.74 Downstream Ports Link PM Latency Register ............................................................... 78
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