Datasheet > XCR5128-15PQ100I

XCR5128-15PQ100I

更新时间： 2024-11-13 03:53:23

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
20页	139K
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128 Macrocell CPLD

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XCR5128-15PQ100I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	PLASTIC, QFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.86	其他特性：	YES
最大时钟频率：	63 MHz	系统内可编程：	YES
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
JTAG BST：	YES	长度：	20 mm
湿度敏感等级：	3	专用输入次数：	2
I/O 线路数量：	80	宏单元数：	128
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2 DEDICATED INPUTS, 80 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	17.5 ns	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

XCR5128-15PQ100I 数据手册

APPLICATION NOTE

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.

XCR5128: 128 Macrocell CPLD

14*

DS041 (v1.4) January 19, 2001

Product Specification

Features

Description

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

The XCR5128 CPLD (Complex Programmable Logic

Device) is the third in a family of CoolRunner^®CPLDs from

Xilinx. These devices combine high speed and zero power

in a 128 macrocell CPLD. With the FZP design technique,

the XCR5128 offers true pin-to-pin speeds of 7.5 ns, while

simultaneously delivering power that is less than 100 µA at

standby without the need for ‘turbo bits' or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than any competing CPLD. These

devices are the first TotalCMOS PLDs, as they use both a

CMOS process technology and the patented full CMOS

FZP design technique. For 3V applications, Xilinx also

offers the high-speed XCR3128 CPLD that offers these fea-

tures in a full 3V implementation.

IEEE 1149.1-compliant, JTAG Testing Capability

Four pin JTAG interface (TCK, TMS, TDI, TDO)

IEEE 1149.1 TAP Controller

JTAG commands include: Bypass, Sample/Preload,

Extest, Usercode, Idcode, HighZ

•

5V, In-System Programmable (ISP) using the JTAG

interface

On-chip supervoltage generation

ISP commands include: Enable, Erase, Program,

Verify

Supported by multiple ISP programming platforms

•

High speed pin-to-pin delays of 7.5 ns

Ultra-low static power of less than 100 µA

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 2 ns,

regardless of the number of PLA product terms used, which

results in worst case t_PD's of only 9.5 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

•

Four clocks available

Programmable clock polarity at every macrocell

Support for asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5µ E²CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

•

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

Programmable 3-state buffer

Asynchronous macrocell register preset/reset

The XCR5128 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-

opsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

•

Programmable global 3-state pin facilitates "bed of

nails" testing without using logic resources

Available in PLCC, VQFP, and PQFP packages

Available in both Commercial and Industrial grades

•

DS041 (v1.4) January 19, 2001

www.xilinx.com

1-800-255-7778

12 3 4 5 6 7...20

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