Datasheet > 可编程逻辑 > 可编程逻辑器件> XCR5128C-10VQ100C

XCR5128C-10VQ100C

更新时间： 2024-09-25 02:52:55

品牌	Logo	应用领域
赛灵思 - XILINX		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
19页	281K
描述
128 Macrocell CPLD with Enhanced Clocking

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

XCR5128C-10VQ100C 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	100
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.35	Is Samacsys：	N
最大时钟频率：	71 MHz	JESD-30 代码：	S-PQFP-G100
长度：	14 mm	专用输入次数：	2
I/O 线路数量：	80	端子数量：	100
最高工作温度：	70 °C	最低工作温度：
组织：	2 DEDICATED INPUTS, 80 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
可编程逻辑类型：	EE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

XCR5128C-10VQ100C 数据手册

浏览型号XCR5128C-10VQ100C的Datasheet PDF文件第2页

浏览型号XCR5128C-10VQ100C的Datasheet PDF文件第3页

浏览型号XCR5128C-10VQ100C的Datasheet PDF文件第4页

浏览型号XCR5128C-10VQ100C的Datasheet PDF文件第5页

浏览型号XCR5128C-10VQ100C的Datasheet PDF文件第6页

浏览型号XCR5128C-10VQ100C的Datasheet PDF文件第7页

APPLICATION NOTE

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.

XCR5128C: 128 Macrocell

CPLD with Enhanced Clocking

14*

DS042 (v1.3) October 9, 2000

Product Specification

Features

Description

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

5V, In-System Programmable (ISP) using a JTAG

interface

The XCR5128C CPLD (Complex Programmable Logic

Device) is a member of the CoolRunner^®family of CPLDs

from Xilinx. These devices combine high speed and zero

power in a 128 macrocell CPLD. With the FZP design tech-

nique, the XCR5128C offers true pin-to-pin speeds of 7.5

ns, while simultaneously delivering power that is less than

100 µA at standby without the need for “turbo bits” or other

power down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology and the pat-

ented full CMOS FZP design technique.

On-chip supervoltage generation

ISP commands include: Enable, Erase, Program,

Verify

Supported by multiple ISP programming platforms

Four pin JTAG interface (TCK, TMS, TDI, TDO)

JTAG commands include: Bypass, Idcode

•

High speed pin-to-pin delays of 7.5 ns

Ultra-low static power of less than 100 µA

100% routable with 100% utilization while all pins and

all macrocells are fixed

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 2ns,

regardless of the number of PLA product terms used, which

results in worst case t_PD's of only 9.5 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

•

Deterministic timing model that is extremely simple to

use

Up to 20 clocks available

Support for complex asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5µ E²CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

•

Programmable 3-state buffer

Asynchronous macrocell register preset/reset

Up to two asynchronous clocks

The XCR5128C CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses Xilinx developed tools including WebFITTER.

•

Programmable global 3-state pin facilitates `bed of

nails' testing without using logic resources

Available in TQFP and LQFP packages

•

Available in both Commercial and Industrial grades

The XCR5128C CPLD is electrically reprogrammable

using industry standard device programmers from vendors

DS042 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

12 3 4 5 6 7...19

中文翻译

下载PDF

与XCR5128C-10VQ100C相关器件

型号	品牌	获取价格	描述	数据表
XCR5128C-10VQ100I	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12TQ128C	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12TQ128I	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12VQ100C	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12VQ100I	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-15TQ128C	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-15TQ128I	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-15VQ100C	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-15VQ100I	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking
XCR5128C-7TQ128C	XILINX	获取价格	128 Macrocell CPLD with Enhanced Clocking

与XCR5128C-10VQ100C相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

6
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

8
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

11
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

17

产品中心

服务支持

精选活动

关于我们

帮助中心

XCR5128C-10VQ100C

XCR5128C-10VQ100C 技术参数

XCR5128C-10VQ100C 数据手册

与XCR5128C-10VQ100C相关器件

与XCR5128C-10VQ100C相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

XCR5128C-10VQ100C

XCR5128C-10VQ100C 技术参数

XCR5128C-10VQ100C 数据手册

与XCR5128C-10VQ100C相关器件

与XCR5128C-10VQ100C相关文章

您还可以找

您在本页遇到什么问题？