Datasheet > XCR5032-10PC44I

XCR5032-10PC44I

更新时间： 2024-11-13 15:58:23

品牌	Logo	应用领域
赛灵思 - XILINX		时钟输入元件可编程逻辑
页数	文件大小	规格书
13页	235K
描述
EE PLD, 10ns, CMOS, PQCC44, PLASTIC, LCC-44

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XCR5032-10PC44I 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	Is Samacsys：	N
最大时钟频率：	59 MHz	JESD-30 代码：	S-PQCC-J44
长度：	16.5862 mm	专用输入次数：	2
I/O 线路数量：	32	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
可编程逻辑类型：	EE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	4.57 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	16.5862 mm
Base Number Matches：	1

XCR5032-10PC44I 数据手册

APPLICATION NOTE

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.

XCR5032: 32 Macrocell CPLD

14*

DS045 (v1.3) October 9, 2000

Product Specification

devices are the first TotalCMOS PLDs, as they use both a

CMOS process technology and the patented full CMOS

FZP design technique. For 3V applications, Xilinx also

offers the high speed XCR3032 CPLD that offers these fea-

tures in a full 3V implementation.

Features

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

•

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

High speed pin-to-pin delays of 6 ns

Ultra-low static power of less than 75 µA

100% routable with 100% utilization while all pins and

all macrocells are fixed

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 6 ns PAL path with five ded-

icated product terms per output. This PAL path is joined by

an additional PLA structure that deploys a pool of 32 prod-

uct terms to a fully programmable OR array that can allo-

cate the PLA product terms to any output in the logic block.

This combination allows logic to be allocated efficiently

throughout the logic block and supports as many as 37

product terms on an output. The speed with which logic is

allocated from the PLA array to an output is only 2 ns,

regardless of the number of PLA product terms used, which

results in worst case t_PD’s of only 8 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

•

Deterministic timing model that is extremely simple to

use

•

Two clocks available

Programmable clock polarity at every macrocell

Support for asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

•

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

•

Advanced 0.5µ E²CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

•

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

The XCR5032 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

Programmable 3-state buffer

Asynchronous macrocell register preset/reset

•

Programmable global 3-state pin facilitates `bed of

nails' testing without using logic resources

•

Available in both PLCC and VQFP packages

Available in both Commercial and Industrial grades

Description

The XCR5032 CPLD is reprogrammable using industry

standard device programmers from vendors such as Data

I/O, BP Microsystems, SMS, and others.

The XCR5032 CPLD (Complex Programmable Logic

Device) is the first in a family of CoolRunner^®CPLDs from

Xilinx. These devices combine high speed and zero power

in a 32 macrocell CPLD. With the FZP design technique,

the XCR5032 offers true pin-to-pin speeds of 6 ns, while

simultaneously delivering power that is less than 75 µA at

standby without the need for "turbo bits" or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than any competing CPLD. These

DS045 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

12 3 4 5 6 7...13

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与XCR5032-10PC44I相关器件

型号	品牌	获取价格	描述	数据表
XCR5032-10VQ44C	XILINX	获取价格	EE PLD, 10ns, CMOS, PQFP44, PLASTIC, VQFP-44
XCR5032-10VQ44I	XILINX	获取价格	EE PLD, 10ns, CMOS, PQFP44, PLASTIC, VQFP-44
XCR5032-6PC44C	XILINX	获取价格	EE PLD, 6ns, CMOS, PQCC44, PLASTIC, LCC-44
XCR5032-6VQ44C	XILINX	获取价格	EE PLD, 6ns, CMOS, PQFP44, PLASTIC, VQFP-44
XCR5032-7PC44C	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQCC44, PLASTIC, LCC-44
XCR5032-7PC44I	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQCC44, PLASTIC, LCC-44
XCR5032-7VQ44C	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQFP44, PLASTIC, VQFP-44
XCR5032C-10PC44I	XILINX	获取价格	EE PLD, 10ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
XCR5032C-10VQ44I	XILINX	获取价格	EE PLD, 10ns, 32-Cell, CMOS, PQFP44, PLASTIC, VQFP-44
XCR5032C-6PC44C	XILINX	获取价格	EE PLD, 6ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44

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