This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.
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XCR5064: 64 Macrocell CPLD
0
14*
DS043 (v1.3) October 9, 2000
Product Specification
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat-
ented full CMOS FZP design technique. For 3V applica-
tions, Xilinx also offers the high speed PZ3064 CPLD that
offers these features in a full 3V implementation.
Features.
•
Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
•
Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
High speed pin-to-pin delays of 7.5 ns
Ultra-low static power of less than 100 µA
100% routable with 100% utilization while all pins and
all macrocells are fixed
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2.0 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD’s of only 9.5 ns from any pin to any
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
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•
•
•
Deterministic timing model that is extremely simple to
use
•
•
•
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Four clocks available
Programmable clock polarity at every macrocell
Support for asynchronous clocking
Innovative XPLA™ architecture combines high speed
with extreme flexibility
•
•
•
•
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
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•
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Advanced 0.5µ E2CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
•
•
Reprogrammable using industry standard device
programmers
Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
The XCR5064 CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
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Programmable 3-state buffer
Asynchronous macrocell register preset/reset
•
Programmable global 3-state pin facilitates `bed of
nails' testing without using logic resources
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Available in PLCC,VQFP, and PQFP packages
Available in both Commercial and Industrial grades
Description
The XCR5064 CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BP Microsystems, SMS, and others.
The XCR5064 CPLD (Complex Programmable Logic
Device) is the second in a family of CoolRunner® CPLDs
from Xilinx. These devices combine high speed and zero
power in a 64 macrocell CPLD. With the FZP design tech-
nique, the XCR5064 offers true pin-to-pin speeds of 7.5 ns,
while simultaneously delivering power that is less than 100
µA at standby without the need for ‘turbo bits’ or other
power down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
DS043 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
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