Datasheet > XC9536XV-7CSG48C

XC9536XV-7CSG48C

更新时间： 2024-11-24 15:58:23

品牌	Logo	应用领域
赛灵思 - XILINX		输入元件可编程逻辑
页数	文件大小	规格书
8页	165K
描述
Flash PLD, 7.5ns, 36-Cell, CMOS, PBGA48, CSP-48

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技术参数
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XC9536XV-7CSG48C 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	FBGA, BGA48,7X7,32
针数：	48	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.66
其他特性：	YES	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B48	JESD-609代码：	e1
JTAG BST：	YES	长度：	7 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	36	宏单元数：	36
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 36 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA48,7X7,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.8/3.3,2.5 V
可编程逻辑类型：	FLASH PLD	传播延迟：	7.5 ns
认证状态：	Not Qualified	座面最大高度：	1.8 mm
子类别：	Programmable Logic Devices	最大供电电压：	2.62 V
最小供电电压：	2.37 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	Base Number Matches：	1

XC9536XV-7CSG48C 数据手册

XC9536XV High-performance

CPLD

DS053 (v2.6) April 15, 2005

Product Specification

For a general estimate of I_CC, the following equation may be

used:

Features

•

36 macrocells with 800 usable gates

Available in small footprint packages

P_TOTAL= P_INT+ P_IO= I_CCINTx V_CCINT+ P_IO

44-pin PLCC (34 user I/O pins)

44-pin VQFP (34 user I/O pins)

48-pin CSP (36 user I/O pins)

Separating internal and I/O power here is convenient

because XC9500XV CPLDs also separate the correspond-

ing power pins. P_IOis a strong function of the load capaci-

tance driven, so it is handled by I = CVf. I_CCINTis another

situation that reflects the actual design considered and the

internal switching speeds. An estimation expression for

•

Optimized for high-performance 2.5V systems

Low power operation

Multi-voltage operation

Advanced system features

I_CCINT(taken from simulation) is:

In-system programmable

I_CCINT(mA) = MC_HS(0.122 X PT_HS+ 0.238) + MC_LP(0.042 x

PT_LP+ 0.171) + 0.04(MC_HS+ MC_LP) x f_MAXx MC_TOG

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

where:

MC_HS= # macrocells used in high speed mode

MC_LP= #macrocells used in low power mode

PT_HS= average p-terms used per high speed macrocell

PT_LP= average p-terms used over low power macrocell

f_MAX= max clocking frequency in the device

MC_TOG= % macrocells toggling on each clock (12% is

frequently a good estimate

This calculation was derived from laboratory measurements

of an XC9500XV part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I_CC

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

application note XAPP361, “Planning for High Speed

XC9500XV Designs.”

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

20 year data retention

ESD protection exceeding 2,000V

•

Pin-compatible with 3.3V-core XC9536XL device in the

44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages

Description

200 MHz

The XC9536XV is a 2.5V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of two

54V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

120 MHz

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XV device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

100

150

200

Clock Frequency (MHz)

DS053_01_121501

Figure 1: Typical I_CCvs. Frequency for XC9536XV

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS053 (v2.6) April 15, 2005

www.xilinx.com

Product Specification

12 3 4 5 6 7 8

中文翻译

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与XC9536XV-7CSG48C相关器件

型号	品牌	获取价格	描述	数据表
XC9536XV-7CSG48I	XILINX	获取价格	Flash PLD, 7.5ns, 36-Cell, CMOS, PBGA48, CSP-48
XC9536XV-7PC44C	XILINX	获取价格	High-performance CPLD
XC9536XV-7PC44I	XILINX	获取价格	High-performance CPLD
XC9536XV-7PCG44C	XILINX	获取价格	Flash PLD, 7.5ns, 36-Cell, CMOS, PQCC44, PLASTIC, LCC-44
XC9536XV-7PCG44I	XILINX	获取价格	Flash PLD, 7.5ns, 36-Cell, CMOS, PQCC44, PLASTIC, LCC-44
XC9536XV-7VQ44C	XILINX	获取价格	High-performance CPLD
XC9536XV-7VQ44I	XILINX	获取价格	High-performance CPLD
XC9536XV-7VQG44C	XILINX	获取价格	Flash PLD, 7.5ns, 36-Cell, CMOS, PQFP44, VQFP-44
XC9536XV-7VQG44I	XILINX	获取价格	Flash PLD, 7.5ns, 36-Cell, CMOS, PQFP44, VQFP-44
XC9536XVSERIES	ETC	获取价格	High-performance CPLD

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