5秒后页面跳转
捷配首页

Datasheet > XC9536XV-7PCG44C
XC9536XV-7PCG44C PDF预览

XC9536XV-7PCG44C

更新时间： 2024-11-24 15:58:23
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
8页 165K
描述
Flash PLD, 7.5ns, 36-Cell, CMOS, PQCC44, PLASTIC, LCC-44

阅读下载

中文翻译

获取价格

XC9536XV-7PCG44C 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：LCC包装说明：QCCJ, LDCC44,.7SQ
针数：44Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.66
其他特性：YES系统内可编程：YES
JESD-30 代码：S-PQCC-J44JESD-609代码：e3
JTAG BST：YES长度：16.5862 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：34宏单元数：36
端子数量：44最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 34 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC44,.7SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：245电源：1.8/3.3,2.5 V
可编程逻辑类型：FLASH PLD传播延迟：7.5 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Programmable Logic Devices最大供电电压：2.62 V
最小供电电压：2.37 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：16.5862 mmBase Number Matches：1

XC9536XV-7PCG44C 数据手册

 浏览型号XC9536XV-7PCG44C的Datasheet PDF文件第2页浏览型号XC9536XV-7PCG44C的Datasheet PDF文件第3页浏览型号XC9536XV-7PCG44C的Datasheet PDF文件第4页浏览型号XC9536XV-7PCG44C的Datasheet PDF文件第5页浏览型号XC9536XV-7PCG44C的Datasheet PDF文件第6页浏览型号XC9536XV-7PCG44C的Datasheet PDF文件第7页 
0
R
XC9536XV High-performance  
CPLD  
0
1
DS053 (v2.6) April 15, 2005  
Product Specification  
For a general estimate of ICC, the following equation may be  
used:  
Features  
•
•
36 macrocells with 800 usable gates  
Available in small footprint packages  
PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO  
-
-
-
44-pin PLCC (34 user I/O pins)  
44-pin VQFP (34 user I/O pins)  
48-pin CSP (36 user I/O pins)  
Separating internal and I/O power here is convenient  
because XC9500XV CPLDs also separate the correspond-  
ing power pins. PIO is a strong function of the load capaci-  
tance driven, so it is handled by I = CVf. ICCINT is another  
situation that reflects the actual design considered and the  
internal switching speeds. An estimation expression for  
•
•
Optimized for high-performance 2.5V systems  
-
-
Low power operation  
Multi-voltage operation  
Advanced system features  
ICCINT (taken from simulation) is:  
-
-
In-system programmable  
ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x  
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG  
Superior pin-locking and routability with  
Fast CONNECT™ II switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
Local clock inversion with three global and one  
product-term clocks  
Individual output enable per output pin  
Input hysteresis on all user and boundary-scan pin  
inputs  
Bus-hold circuitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
where:  
-
-
MCHS = # macrocells used in high speed mode  
MCLP = #macrocells used in low power mode  
-
PTHS = average p-terms used per high speed macrocell  
PTLP = average p-terms used over low power macrocell  
-
-
fMAX = max clocking frequency in the device  
MCTOG = % macrocells toggling on each clock (12% is  
frequently a good estimate  
-
-
This calculation was derived from laboratory measurements  
of an XC9500XV part filled with 16-bit counters and allowing  
a single output (the LSB) to be enabled. The actual ICC  
value varies with the design application and should be veri-  
fied during normal system operation. Figure 1 shows the  
above estimation in a graphical form. For a more detailed  
discussion of power consumption in this device, see Xilinx  
application note XAPP361, “Planning for High Speed  
XC9500XV Designs.”  
•
•
•
•
Fast concurrent programming  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
•
Pin-compatible with 3.3V-core XC9536XL device in the  
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages  
Description  
60  
200 MHz  
The XC9536XV is a 2.5V CPLD targeted for high-perfor-  
mance, low-voltage applications in leading-edge communi-  
cations and computing systems. It is comprised of two  
54V18 Function Blocks, providing 800 usable gates with  
propagation delays of 5 ns. See Figure 2 for architecture  
overview.  
50  
40  
120 MHz  
30  
20  
10  
Power Estimation  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XV device may be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
0
50  
100  
150  
200  
Clock Frequency (MHz)  
DS053_01_121501  
Figure 1: Typical ICC vs. Frequency for XC9536XV  
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS053 (v2.6) April 15, 2005  
www.xilinx.com  
1
Product Specification  
12345678

中文翻译

下载PDF

与XC9536XV-7PCG44C相关器件

型号 品牌 获取价格 描述 数据表
XC9536XV-7PCG44I XILINX

获取价格

 		Flash PLD, 7.5ns, 36-Cell, CMOS, PQCC44, PLASTIC, LCC-44
XC9536XV-7VQ44C XILINX

获取价格

 		High-performance CPLD
XC9536XV-7VQ44I XILINX

获取价格

 		High-performance CPLD
XC9536XV-7VQG44C XILINX

获取价格

 		Flash PLD, 7.5ns, 36-Cell, CMOS, PQFP44, VQFP-44
XC9536XV-7VQG44I XILINX

获取价格

 		Flash PLD, 7.5ns, 36-Cell, CMOS, PQFP44, VQFP-44
XC9536XVSERIES ETC

获取价格

 		High-performance CPLD
XC95432-10BG432C XILINX

获取价格

 		Flash PLD, 10ns, CMOS, PBGA432, BGA-432
XC95432-10BGG432C XILINX

获取价格

 		Flash PLD, 10ns, CMOS, PBGA432, BGA-432
XC95432-10HQ304 XILINX

获取价格

 		Flash PLD, CMOS, PQFP304, 40 X 40 MM, METRIC, HEAT SINK, EIAJ, PLASTIC, MO-143JA, QFP-304
XC95432-10HQ304C XILINX

获取价格

 		Flash PLD, 10ns, CMOS, PQFP304, HEAT SINK, PLASTIC, QFP-304

与XC9536XV-7PCG44C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证