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XC9536XV-3VQG44C PDF预览

XC9536XV-3VQG44C

更新时间: 2024-11-20 15:58:23
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
8页 67K
描述
Flash PLD, 3.5ns, PQFP44, PLASTIC, VQFP-44

XC9536XV-3VQG44C 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, VQFP-44
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.66
JESD-30 代码:S-PQFP-G44JESD-609代码:e3
长度:10 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:34
端子数量:44最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 34 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):260
可编程逻辑类型:FLASH PLD传播延迟:3.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:2.62 V最小供电电压:2.37 V
标称供电电压:2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

XC9536XV-3VQG44C 数据手册

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0
R
XC9536XV High-performance  
CPLD  
0
1
DS053 (v2.2) August 27, 2001  
Advance Product Specification  
Features  
Power Estimation  
36 macrocells with 800 usable gates  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XV device may be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
Available in small footprint packages  
-
-
-
44-pin PLCC (34 user I/O pins)  
44-pin VQFP (34 user I/O pins)  
48-pin CSP (36 user I/O pins)  
Optimized for high-performance 2.5V systems  
-
-
Low power operation  
Multi-voltage operation  
For a general estimate of I , the following equation may be  
CC  
used:  
Advanced system features  
I
(mA) =  
CC  
-
-
In-system programmable  
Superior pin-locking and routability with  
FastCONNECT II™ switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
MC (0.36) + MC (0.23) + MC(0.005 mA/MHz) f  
HP LP  
Where:  
MC = Macrocells in high-performance (default) mode  
-
-
HP  
MC = Macrocells in low-power mode  
LP  
-
Local clock inversion with three global and one  
product-term clocks  
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
-
-
Individual output enable per output pin  
Input hysteresis on all user and boundary-scan pin  
inputs  
This calculation is based on typical operating conditions  
using a pattern of 16-bit up/down counters in each Function  
-
-
Bus-hold circuitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Block with no output loading. The actual I  
value varies  
CC  
with the design application and should be verified during  
normal system operation.  
Fast concurrent programming  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
Figure 1 shows the above estimation in a graphical form.  
60  
-
Endurance exceeding 10,000 program/erase  
cycles  
50  
200 MHz  
40  
30  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
Pin-compatible with 3.3V-core XC9536XL device in the  
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages  
120 MHz  
20  
Description  
10  
The XC9536XV is a 2.5V CPLD targeted for high-perfor-  
mance, low-voltage applications in leading-edge communi-  
cations and computing systems. It is comprised of two  
54V18 Function Blocks, providing 800 usable gates with  
propagation delays of 3.5 ns. See Figure 2 for architecture  
overview.  
0
50  
100  
150  
200  
Clock Frequency (MHz)  
DS053_01_012501  
Figure 1: Typical I vs. Frequency for XC9536XV  
CC  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS053 (v2.2) August 27, 2001  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  

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