Datasheet > XC9536SERIES

XC9536SERIES

更新时间： 2024-11-19 23:32:31

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赛灵思 - XILINX		/
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描述
In-System Programmable CPLD

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中文翻译

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数据手册

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XC9536SERIES 数据手册

XC9536 In-System Programmable

CPLD

December 4, 1998 (Version 5.0)

Product Specification

Features

Power Management

•

5 ns pin-to-pin logic delays on all pins

to 100 MHz

Power dissipation can be reduced in the XC9536 by config-

uring macrocells to standard or low-power modes of opera-

tion. Unused macrocells are turned off to minimize power

dissipation.

CNT

•

36 macrocells with 800 usable gates

Up to 34 user I/O pins

5 V in-system programmable (ISP)

Operating current for each design can be approximated for

specific operating conditions using the following equation:

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

(mA) =

•

Enhanced pin-locking architecture

Flexible 36V18 Function Block

(1.7) + MC (0.9) + MC (0.006 mA/MHz) f

HP LP

Where:

90 product terms drive any or all of 18 macrocells

within Function Block

= Macrocells in high-performance mode

Global and product term clocks, output enables, set

and reset signals

MC = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

•

Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

Programmable power reduction mode in each

macrocell

Figure 1 shows a typical calculation for the XC9536 device.

•

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design protection

High-drive 24 mA outputs

(83)

3.3 V or 5 V I/O capability

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one

XC9500 concurrently

(50)

•

Available in 44-pin PLCC, 44-pin VQFP, and 48-pin

CSP packages

(30)

Description

The XC9536 is a high-performance CPLD providing

advanced in-system programming and test capabilities for

general purpose logic integration. It is comprised of two

36V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See Figure 2 for the architec-

ture overview.

100

Clock Frequency (MHz)

X5920

Figure 1: Typical I

vs. Frequency For XC9536

December 4, 1998 (Version 5.0)

12 3 4 5 6 7

中文翻译

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与XC9536SERIES相关器件

型号	品牌	获取价格	描述	数据表
XC9536XL	XILINX	获取价格	XC9536XL High PerformanceCPLD
XC9536XL-10CS48C	XILINX	获取价格	XC9536XL High PerformanceCPLD
XC9536XL-10CS48I	XILINX	获取价格	XC9536XL High PerformanceCPLD
XC9536XL-10CSG48I	XILINX	获取价格	Flash PLD, 10ns, 36-Cell, CMOS, PBGA48, LEAD FREE, CSP-48
XC9536XL-10PC44C	XILINX	获取价格	XC9536XL High PerformanceCPLD
XC9536XL-10PC44I	XILINX	获取价格	XC9536XL High PerformanceCPLD
XC9536XL-10PCG44C	XILINX	获取价格	Flash PLD, 10ns, 36-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44
XC9536XL-10PCG44I	XILINX	获取价格	Flash PLD, 10ns, 36-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44
XC9536XL-10VQ44C	XILINX	获取价格	XC9536XL High PerformanceCPLD
XC9536XL-10VQ44I	XILINX	获取价格	XC9536XL High PerformanceCPLD

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