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XC9536XL-10VQG44Q

更新时间： 2024-11-21 10:57:43
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
22页 183K
描述
Flash PLD, 10ns, CMOS, PQFP44, PLASTIC, VQFP-44

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XC9536XL-10VQG44Q 数据手册

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XC9500XL High-Performance  
CPLD Automotive IQ Product  
Family  
R
0
0
DS108 (v1.0) June 17, 2002  
Advance Product Specification  
Features  
Description  
•
Guaranteed to meet full electrical specifications over  
TA = –40°C to +125°C  
The XC9500XL 3.3V CPLD Automotive IQ product family is  
targeted for leading-edge, high-performance, low-voltage  
automotive (–40°C to +125°C) applications.  
•
•
•
System frequency up to 100 MHz (10 ns)  
Available in small footprint packages  
Power Estimation  
Optimized for high-performance 3.3V systems  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in the XC9500XL device can be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V  
signals — ideal for multi-voltage system interfacing  
and level shifting  
-
Technology: 0.35µm CMOS process  
•
Advanced system features  
-
In-system programmable enabling higher system  
reliability through reduced handling and reducing  
production programming times  
For a general estimate of ICC, the following equation may be  
used:  
-
Superior pin-locking and routability with  
FastCONNECT™ II switch matrix allowing for  
multiple design iterations without board re-spins  
Input hysteresis on all user and boundary-scan pin  
inputs to reduce noise on input signals  
Bus-hold circuitry on all user pin inputs which  
reduces cost associated with pull-up resistors and  
reduces bus loading  
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f  
where:  
-
-
MCHP = Macrocells in high-performance (default)  
mode  
MCLP = Macrocells in low-power mode  
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
for in-system device testing  
·
Fast concurrent programming  
This calculation is based on typical operating conditions  
using a pattern of 16-bit up/down counters in each Function  
Block with no output loading. The actual ICC value varies  
with the design application and should be verified during  
normal system operation.  
•
Slew rate control on individual outputs for reducing EMI  
generation  
.
Table 1: XC9500XL Device Family  
Device  
Macrocells  
Usable Gates  
800  
Registers  
fSYSTEM (MHz)  
XC9536XL  
XC9572XL  
36  
72  
36  
72  
100  
100  
1,600  
Table 2: XC9500XL Packages and User I/O Pins (not including four dedicated JTAG pins)  
Device  
VQ44  
VQ64  
36  
TQ100  
XC9536XL  
XC9572XL  
34  
-
-
52  
72  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS108 (v1.0) June 17, 2002  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
1234567...22

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