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XC9536XL-4PC44C PDF预览

XC9536XL-4PC44C

更新时间： 2024-11-19 22:52:03
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
7页 312K
描述
XC9536XL High PerformanceCPLD

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中文翻译

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XC9536XL-4PC44C 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-44
针数：44Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.7Is Samacsys：N
其他特性：36 MACROCELLS最大时钟频率：200 MHz
系统内可编程：YESJESD-30 代码：S-PQCC-J44
JESD-609代码：e0JTAG BST：YES
长度：16.5862 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：34
宏单元数：36端子数量：44
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 34 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC44,.7SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：2.5/3.3,3.3 V可编程逻辑类型：FLASH PLD
传播延迟：4 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：16.5862 mm
Base Number Matches：1

XC9536XL-4PC44C 数据手册

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R
XC9536XL High Performance  
CPLD  
DS058 (v1.2) June 25, 2001  
Preliminary Product Specification  
cations and computing systems. It is comprised of two  
54V18 Function Blocks, providing 800 usable gates with  
propagation delays of 5 ns. See Figure 2 for architecture  
overview.  
Features  
•
•
•
•
5 ns pin-to-pin logic delays  
System frequency up to 178 MHz  
36 macrocells with 800 usable gates  
Available in small footprint packages  
Power Estimation  
-
-
-
-
44-pin PLCC (34 user I/O pins)  
44-pin VQFP (34 user I/O pins)  
48-pin CSP (36 user I/O pins)  
64-pin VQFP (36 user I/O pins)  
Power dissipation in CPLDs can vary substantially depend•  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XL device may be configured for low-power  
mode (from the default high-performance mode). In addi•  
tion, unused product-terms and macrocells are automati•  
cally deactivated by the software to further conserve power.  
•
•
Optimized for high-performance 3.3V systems  
-
-
Low power operation  
5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V  
signals  
For a general estimate of I , the following equation may be  
CC  
-
-
3.3V or 2.5V output capability  
Advanced 0.35 micron feature size CMOS  
FastFLASH™ technology  
used:  
I
(mA) = MC (0.5) + MC (0.3) + MC(0.0045 mA/MHz) f  
HP LP  
CC  
Where:  
MC = Macrocells in high-performance (default) mode  
Advanced system features  
-
-
In-system programmable  
HP  
Superior pin-locking and routability with  
FastCONNECT II™ switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
Local clock inversion with three global and one  
product-term clocks  
MC = Macrocells in low-power mode  
LP  
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
-
-
This calculation is based on typical operating conditions  
using a pattern of 16-bit up/down counters in each Function  
-
Block with no output loading. The actual I  
value varies  
CC  
-
-
Individual output enable per output pin  
Input hysteresis on all user and boundary-scan pin  
inputs  
with the design application and should be verified during  
normal system operation.  
Figure 1 shows the above estimation in a graphical form.  
-
-
Bus-hold circuitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
60  
•
•
•
•
Fast concurrent programming  
178 MHz  
50  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
40  
30  
-
Endurance exceeding 10,000 program/erase  
cycles  
125 MHz  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
20  
•
Pin-compatible with 5V-core XC9536 device in the  
44-pin PLCC package and the 48-pin CSP package  
10  
Description  
0
100  
200  
250  
50  
150  
The XC9536XL is a 3.3V CPLD targeted for high-perfor•  
mance, low-voltage applications in leading-edge communi•  
Clock Frequency (MHz)  
DS058_01_061101  
Figure 1: Typical I vs. Frequency for XC9536XL  
CC  
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS058 (v1.2) June 25, 2001  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234567

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