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XC2S200-5FG456I

更新时间： 2024-11-08 03:53:39

品牌	Logo	应用领域
赛灵思 - XILINX		可编程逻辑栅时钟
页数	文件大小	规格书
4页	44K
描述
Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

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XC2S200-5FG456I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	BGA, BGA456,22X22,40	针数：	456
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.D
HTS代码：	8542.39.00.01	风险等级：	1.54
最大时钟频率：	263 MHz	CLB-Max的组合延迟：	0.7 ns
JESD-30 代码：	S-PBGA-B456	JESD-609代码：	e0
长度：	23 mm	湿度敏感等级：	3
可配置逻辑块数量：	1176	等效关口数量：	200000
输入次数：	288	逻辑单元数量：	5292
输出次数：	284	端子数量：	456
组织：	1176 CLBS, 200000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA456,22X22,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	225	电源：	1.5/3.3,2.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.6 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	2.625 V	最小供电电压：	2.375 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	23 mm	Base Number Matches：	1

XC2S200-5FG456I 数据手册

Spartan-II 2.5V FPGA Family:

Introduction and Ordering

Information

DS001-1 (v2.3) November 1, 2001

Preliminary Product Specification

•

System level features

Introduction

SelectRAM+™ hierarchical memory:

The Spartan™-II 2.5V Field-Programmable Gate Array fam-

ily gives users high performance, abundant logic resources,

and a rich feature set, all at an exceptionally low price. The

six-member family offers densities ranging from 15,000 to

200,000 system gates, as shown in Table 1. System perfor-

mance is supported up to 200 MHz.

16 bits/LUT distributed RAM

Configurable 4K bit block RAM

Fast interfaces to external RAM

Fully PCI compliant

Low-power segmented routing architecture

Full readback ability for verification/observability

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with enable, set, reset

Four dedicated DLLs for advanced clock control

Four primary low-skew global clock distribution nets

IEEE 1149.1 compatible boundary scan logic

Spartan-II devices deliver more gates, I/Os, and features

per dollar than other FPGAs by combining advanced pro-

cess technology with a streamlined Virtex-based architec-

ture. Features include block RAM (to 56K bits), distributed

RAM (to 75,264 bits), 16 selectable I/O standards, and four

DLLs. Fast, predictable interconnect means that successive

design iterations continue to meet timing requirements.

The Spartan-II family is

superior alternative to

•

Versatile I/O and packaging

mask-programmed ASICs. The FPGA avoids the initial cost,

lengthy development cycles, and inherent risk of

conventional ASICs. Also, FPGA programmability permits

design upgrades in the field with no hardware replacement

necessary (impossible with ASICs).

Low cost packages available in all densities

Family footprint compatibility in common packages

16 high-performance interface standards

Hot swap Compact PCI friendly

Zero hold time simplifies system timing

Features

Fully supported by powerful Xilinx development system

Foundation ISE Series: Fully integrated software

Alliance Series: For use with third-party tools

Fully automatic mapping, placement, and routing

•

Second generation ASIC replacement technology

Densities as high as 5,292 logic cells with up to

200,000 system gates

Streamlined features based on Virtex architecture

Unlimited reprogrammability

Very low cost

Table 1: Spartan-II FPGA Family Members

CLB

Array

(R x C)

Maximum

Available

User I/O

Total

Distributed RAM

Bits

Total

Block RAM

Bits

Logic

Cells

System Gates

(Logic and RAM)

Total

CLBs

(1)

Device

XC2S15

XC2S30

XC2S50

XC2S100

XC2S150

XC2S200

432

972

15,000

30,000

8 x 12

12 x 18

16 x 24

20 x 30

24 x 36

28 x 42

6,144

13,824

24,576

38,400

55,296

75,264

16K

24K

32K

40K

48K

56K

216

132

176

196

260

284

1,728

2,700

3,888

5,292

50,000

384

100,000

150,000

200,000

600

864

1,176

Notes:

1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS001-1 (v2.3) November 1, 2001

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

12 3 4

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XC2S200-5FG456I 替代型号

型号	品牌	替代类型	描述	数据表
XC2S200-5PQG208I	XILINX	完全替代	Spartan-II FPGA Family
XC2S200-6FG456C	XILINX	完全替代	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S200-5FG456C	XILINX	完全替代	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

与XC2S200-5FG456I相关器件

型号	品牌	获取价格	描述	数据表
XC2S200-5FGG256C	XILINX	获取价格	Spartan-II FPGA Family
XC2S200-5FGG256I	XILINX	获取价格	Spartan-II FPGA Family
XC2S200-5FGG456C	XILINX	获取价格	Spartan-II FPGA Family
XC2S200-5FGG456I	XILINX	获取价格	Spartan-II FPGA Family
XC2S200-5FGG456Q	XILINX	获取价格	Field Programmable Gate Array, 864 CLBs, 200000 Gates, PBGA456, FBGA-456
XC2S200-5PQ208C	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S200-5PQ208I	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S200-5PQ208Q	XILINX	获取价格	暂无描述
XC2S200-5PQG208C	XILINX	获取价格	Spartan-II FPGA Family
XC2S200-5PQG208I	XILINX	获取价格	Spartan-II FPGA Family

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