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XC2S100-6TQ144C

更新时间： 2024-11-08 03:23:59
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赛灵思 - XILINX 现场可编程门阵列可编程逻辑栅时钟
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4页 44K
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Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

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XC2S100-6TQ144C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Not Recommended零件包装代码：QFP
包装说明：PLASTIC, TQFP-144针数：144
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.28Is Samacsys：N
其他特性：MAXIMUM USABLE GATES 100000最大时钟频率：263 MHz
CLB-Max的组合延迟：0.6 nsJESD-30 代码：S-PQFP-G144
JESD-609代码：e0长度：20 mm
湿度敏感等级：3可配置逻辑块数量：600
等效关口数量：100000输入次数：96
逻辑单元数量：2700输出次数：92
端子数量：144最高工作温度：85 °C
最低工作温度：组织：600 CLBS, 100000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：225
电源：1.5/3.3,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Field Programmable Gate Arrays最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：20 mmBase Number Matches：1

XC2S100-6TQ144C 数据手册

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0
Spartan-II 2.5V FPGA Family:  
Introduction and Ordering  
Information  
R
0
0
DS001-1 (v2.3) November 1, 2001  
Preliminary Product Specification  
•
System level features  
Introduction  
-
SelectRAM+™ hierarchical memory:  
The Spartan™-II 2.5V Field-Programmable Gate Array fam-  
ily gives users high performance, abundant logic resources,  
and a rich feature set, all at an exceptionally low price. The  
six-member family offers densities ranging from 15,000 to  
200,000 system gates, as shown in Table 1. System perfor-  
mance is supported up to 200 MHz.  
·
·
·
16 bits/LUT distributed RAM  
Configurable 4K bit block RAM  
Fast interfaces to external RAM  
-
-
-
-
-
-
-
-
-
-
Fully PCI compliant  
Low-power segmented routing architecture  
Full readback ability for verification/observability  
Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with enable, set, reset  
Four dedicated DLLs for advanced clock control  
Four primary low-skew global clock distribution nets  
IEEE 1149.1 compatible boundary scan logic  
Spartan-II devices deliver more gates, I/Os, and features  
per dollar than other FPGAs by combining advanced pro-  
cess technology with a streamlined Virtex-based architec-  
ture. Features include block RAM (to 56K bits), distributed  
RAM (to 75,264 bits), 16 selectable I/O standards, and four  
DLLs. Fast, predictable interconnect means that successive  
design iterations continue to meet timing requirements.  
The Spartan-II family is  
a
superior alternative to  
•
•
Versatile I/O and packaging  
mask-programmed ASICs. The FPGA avoids the initial cost,  
lengthy development cycles, and inherent risk of  
conventional ASICs. Also, FPGA programmability permits  
design upgrades in the field with no hardware replacement  
necessary (impossible with ASICs).  
-
-
-
-
-
Low cost packages available in all densities  
Family footprint compatibility in common packages  
16 high-performance interface standards  
Hot swap Compact PCI friendly  
Zero hold time simplifies system timing  
Features  
Fully supported by powerful Xilinx development system  
-
-
-
Foundation ISE Series: Fully integrated software  
Alliance Series: For use with third-party tools  
Fully automatic mapping, placement, and routing  
•
Second generation ASIC replacement technology  
-
Densities as high as 5,292 logic cells with up to  
200,000 system gates  
-
-
-
Streamlined features based on Virtex architecture  
Unlimited reprogrammability  
Very low cost  
Table 1: Spartan-II FPGA Family Members  
CLB  
Array  
(R x C)  
Maximum  
Available  
User I/O  
Total  
Distributed RAM  
Bits  
Total  
Block RAM  
Bits  
Logic  
Cells  
System Gates  
(Logic and RAM)  
Total  
CLBs  
(1)  
Device  
XC2S15  
XC2S30  
XC2S50  
XC2S100  
XC2S150  
XC2S200  
432  
972  
15,000  
30,000  
8 x 12  
12 x 18  
16 x 24  
20 x 30  
24 x 36  
28 x 42  
96  
86  
6,144  
13,824  
24,576  
38,400  
55,296  
75,264  
16K  
24K  
32K  
40K  
48K  
56K  
216  
132  
176  
196  
260  
284  
1,728  
2,700  
3,888  
5,292  
50,000  
384  
100,000  
150,000  
200,000  
600  
864  
1,176  
Notes:  
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS001-1 (v2.3) November 1, 2001  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234

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XC2S100-6TQ144C 替代型号

型号 品牌 替代类型 描述 数据表
XC2S100-5TQG144C XILINX

完全替代

 Spartan-II FPGA Family
XC2S100-6TQG144C XILINX

完全替代

 Spartan-II FPGA Family
XC2S100-5TQ144C XILINX

完全替代

 Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

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