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X9268US24-2.7

更新时间: 2024-10-31 22:25:11
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
24页 367K
描述
Dual Supply/Low Power/256-Tap/2-Wire Bus

X9268US24-2.7 数据手册

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X9268  
®
Dual Supply/Low Power/256-Tap/2-Wire Bus  
Data Sheet  
June 21, 2005  
FN8172.1  
DESCRIPTION  
Dual Digitally-Controlled (XDCP™)  
Potentiometers  
The X9268 integrates  
potentiometer (XDCP) on  
integrated circuit.  
2
digitally controlled  
monolithic CMOS  
a
FEATURES  
• Dual–Two separate potentiometers  
• 256 resistor taps/pot–0.4% resolution  
• 2-Wire Serial Interface for write, read, and  
transfer operations of the potentiometer  
Wiper Resistance, 100typical @ V+ = 5V,  
V- = -5V  
• 16 Nonvolatile Data Registers for Each  
Potentiometer  
• Nonvolatile Storage of Multiple Wiper Positions  
• Power-on Recall. Loads Saved Wiper Position  
on Power-up.  
The digital controlled potentiometer is implemented  
using 255 resistive elements in a series array.  
Between each element are tap points connected to the  
wiper terminal through switches. The position of the  
wiper on the array is controlled by the user through the  
2-Wire bus interface. Each potentiometer has  
associated with it a volatile Wiper Counter Register  
(WCR) and a four nonvolatile Data Registers that can  
be directly written to and read by the user. The  
contents of the WCR controls the position of the wiper  
on the resistor array though the switches. Powerup  
recalls the contents of the default Data Register (DR0)  
to the WCR.  
• Standby Current < 5µA Max  
• V : ±2.7V to ±5.5V Operation  
CC  
• 50k, 100kversions of End to End Pot  
Resistance  
The XDCP can be used as  
a three-terminal  
• Endurance: 100,000 Data Changes per Bit per  
Register  
• 100 yr. Data Retention  
potentiometer or as a two terminal variable resistor in  
a wide variety of applications including control,  
parameter adjustments, and signal processing.  
• 24-Lead SOIC, 24-Lead TSSOP  
• Low Power CMOS  
• Power Supply V  
= ±2.7V to ±5.5V  
CC  
V+ = 2.7V to 5.5V  
V- = -2.7V to -5.5V  
FUNCTIONAL DIAGRAM  
V
R
R
H1  
V
CC  
H0  
+
Write  
Read  
Transfer  
Inc/Dec  
Address  
Data  
Status  
Power-on Recall  
Bus  
2-Wire  
Bus  
Interface  
Wiper Counter  
Registers (WCR)  
Interface  
and Control  
Data Registers  
(DR0–DR3)  
Control  
V
R
R
R
R
V-  
SS  
W0  
L0  
W1  
L1  
50kΩ  
or 100kversions  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
1

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