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X28HC256SM-12 PDF预览

X28HC256SM-12

更新时间: 2024-11-20 12:17:15
品牌 Logo 应用领域
XICOR 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 112K
描述
5 Volt, Byte Alterable E2PROM

X28HC256SM-12 数据手册

 浏览型号X28HC256SM-12的Datasheet PDF文件第2页浏览型号X28HC256SM-12的Datasheet PDF文件第3页浏览型号X28HC256SM-12的Datasheet PDF文件第4页浏览型号X28HC256SM-12的Datasheet PDF文件第5页浏览型号X28HC256SM-12的Datasheet PDF文件第6页浏览型号X28HC256SM-12的Datasheet PDF文件第7页 
256K  
X28HC256  
5 Volt, Byte Alterable E2PROM  
DESCRIPTION  
32K x 8 Bit  
FEATURES  
Access Time: 70ns  
Simple Byte and Page Write  
Single 5V Supply  
The X28HC256 is a second generation high perfor-  
mance CMOS 32K x 8 E PROM. It is fabricated with  
Xicor’s proprietary, textured poly floating gate tech-  
nology, providing a highly reliable 5 Volt only nonvolatile  
memory.  
2
No External High Voltages or V Control  
PP  
Circuits  
Self-Timed  
The X28HC256 supports a 128-byte page write opera-  
tion, effectively providing a 24µs/byte write cycle and  
enabling the entire memory to be typically rewritten in  
less than 0.8 seconds. The X28HC256 also features  
DATA Polling and Toggle Bit Polling, two methods of  
providing early end of write detection. The X28HC256  
also supports the JEDEC standard Software Data Pro-  
tection feature for protecting against inadvertent writes  
during power-up and power-down.  
No Erase Before Write  
No Complex Programming Algorithms  
—No Overerase Problem  
Low Power CMOS:  
Active: 60mA  
Standby: 500µA  
Software Data Protection  
Protects Data Against System Level  
Inadvertent Writes  
High Speed Page Write Capability  
EndurancefortheX28HC256isspecifiedasaminimum  
100,000 write cycles per byte and an inherent data  
retention of 100 years.  
Highly Reliable Direct Write Cell  
Endurance: 100,000 Write Cycles  
Data Retention: 100 Years  
Early End of Write Detection  
DATA Polling  
Toggle Bit Polling  
PIN CONFIGURATION  
PLASTIC DIP  
CERDIP  
FLAT PACK  
SOIC  
LCC  
PLCC  
A14  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
TSOP  
A
2
3
4
5
6
7
8
9
WE  
12  
4
3
2
1
32 31 30  
A
A
A
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
A
A
A
A
A
NC  
V
NC  
WE  
2
1
0
0
1
2
3
4
5
6
7
12  
14  
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
13  
A
A
A
A
A
A
A
5
6
7
8
9
29  
28  
27  
26  
25  
24  
23  
22  
21  
A
A
A
6
5
4
3
2
1
0
8
A
8
A
9
9
11  
A
11  
NC  
OE  
A
NC  
OE  
X28HC256  
X28HC256  
V
SS  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
X28HC256  
A
10  
9
CC  
10  
11  
12  
13  
10  
10  
11  
12  
13  
14  
15  
16  
CE  
3
4
5
6
7
CE  
10  
11  
12  
13  
14  
I/O  
7
I/O  
6
I/O  
5
I/0  
4
A
A
A
A
13  
8
9
NC  
I/O  
I/O  
7
I/O  
0
I/O  
1
I/O  
2
I/O  
0
6
14 15 16 17 18 19 20  
CE  
11  
A
OE  
10  
V
I/O  
3
SS  
3859 ILL F22  
3859 FHD F03  
3859 FHD F02  
©Xicor, Inc. 1991, 1995 Patents Pending  
3859-2.8 8/5/97 T1/C0/D0 EW  
Characteristics subject to change without notice  
1

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