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X24012SI-3T1 PDF预览

X24012SI-3T1

更新时间: 2024-11-13 15:58:07
品牌 Logo 应用领域
XICOR 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
13页 141K
描述
EEPROM, 128X8, Serial, CMOS, PDSO8, PLASTIC, SOIC-8

X24012SI-3T1 技术参数

生命周期:Obsolete包装说明:PLASTIC, SOIC-8
Reach Compliance Code:unknown风险等级:5.84
其他特性:2 WIRE INTERFACE;PAGE WRITE最大时钟频率 (fCLK):0.1 MHz
JESD-30 代码:R-PDSO-G8长度:4.9 mm
内存密度:1024 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:128 words
字数代码:128工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128X8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
认证状态:Not Qualified座面最大高度:1.75 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

X24012SI-3T1 数据手册

 浏览型号X24012SI-3T1的Datasheet PDF文件第2页浏览型号X24012SI-3T1的Datasheet PDF文件第3页浏览型号X24012SI-3T1的Datasheet PDF文件第4页浏览型号X24012SI-3T1的Datasheet PDF文件第5页浏览型号X24012SI-3T1的Datasheet PDF文件第6页浏览型号X24012SI-3T1的Datasheet PDF文件第7页 
Preliminary Information  
Pin 7 No Connect  
1K  
X24012  
128 x 8 Bit  
Serial E2PROM  
FEATURES  
DESCRIPTION  
2
2.7 to 5.5V Power Supply  
The X24012 is a CMOS 1024 bit serial E PROM,  
internally organized as one 128 x 8 bank. The X24012  
features a serial interface and software protocol allow-  
ing operation on a simple two wire bus. Three address  
inputs allow up to eight devices to share a common two  
wire bus.  
Low Power CMOS  
—Active Current Less Than 1 mA  
—Standby Current Less Than 50 µA  
Internally Organized 128 x 8  
Self Timed Write Cycle  
—Typical Write Cycle Time of 5 ms  
2 Wire Serial Interface  
2
Xicor E PROMs are designed and tested for applica-  
tions requiring extended endurance. Inherent data re-  
tention is greater than 100 years. The X24012 is avail-  
able in eight pin DIP and SOIC packages.  
—Bidirectional Data Transfer Protocol  
Four Byte Page Write Operation  
—Minimizes Total Write Time Per Byte  
High Reliability  
—Endurance: 100,000 Cycles  
—Data Retention: 100 Years  
FUNCTIONAL DIAGRAM  
(8) V  
(4) V  
CC  
SS  
H.V. GENERATION  
START CYCLE  
TIMING  
& CONTROL  
START  
STOP  
(5) SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER  
+COMPARATOR  
2
E PROM  
XDEC  
32 X 32  
LOAD  
INC  
(6) SCL  
(3) A  
2
WORD  
ADDRESS  
COUNTER  
(2) A  
(1) A  
1
0
R/W  
YDEC  
8
CK  
D
OUT  
PIN  
DATA REGISTER  
D
OUT  
ACK  
3847 FHD F01  
© Xicor, 1991 Patents Pending  
3847-1  
Characteristics subject to change without notice  
1

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