Datasheet > 存储 > SRAM> WS512K16-25DLC

WS512K16-25DLC

更新时间： 2024-11-30 03:16:07

品牌	Logo	应用领域
WEDC		存储静态存储器
页数	文件大小	规格书
6页	322K
描述
512Kx16 SRAM MODULE

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中文翻译

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数据手册

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WS512K16-25DLC 数据手册

WS512K16-XXX

White Electronic Designs

ADVANCED*

512Kx16 SRAM MODULE

FEATURES

ꢀ

Data I/O Compatible with 3.3V devices

ꢀ

Access Times 17, 20, 25, 35ns

2V Minimum Data Retention for battery back up

operation

MIL-STD-883 Compliant Devices Available

Packaging

ꢀ

Commercial, Industrial and Military Temperature

Range

• 44 pin Ceramic SOJ (Package 102)

• 44 lead Ceramic Flatpack (Package 209)

Organized as two banks of 256Kx16

Data Byte Control:

ꢀ

5 Volt Power Supply (3.3V parts also available)

Low Power CMOS

ꢀ

TTL Compatible Inputs and Outputs

Lower Byte (LB#) = I/O1-8

Upper Byte (UB#) = I/O9-16

* This product is under development, is not qualiﬁed or characterized and is subject to

change or cancellation without notice.

PIN CONFIGURATION FOR WS512K16-XXX

Pin Description

44 CSOJ

A0-17

LB#

UB#

I/O1-16

CS1-2#

OE#

WE#

V_CC

Address Inputs

Lower-Byte Control (I/O1-8)

Upper-Byte Control (I/O9-16)

Data Input/Output

Chip Select

44 FLATPACK

Top View

A17

A16

A15

Output Enable

Write Enable

+5.0V Power

Ground

OE#

UB#

LB#

I/O16

I/O15

I/O14

I/O13

GND

V_CC

I/O12

I/O11

I/O10

I/O9

CS2#

A14

CS1#

I/O1

I/O2

I/O3

I/O4

V_CC

GND

I/O5

I/O6

I/O7

I/O8

WE#

GND

No Connection

Block Diagram

0-17

WE#

OE#

UB#

LB#

A13

A12

A11

A10

256K x 16

CS1#

CS2#

I/O1-16

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

April 1998

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6

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