WF128K16, WF256K16-XCX5
5V FLASH MODULE
PRELIMINARY *
FEATURES
■ Access Times of 50, 60, 70, 90, 120 and 150ns
■ 5 Volt Programming; 5V ±10% Supply
■ 40 pin Ceramic DIP (Package 303)
■ Low Power CMOS
■ Organized as 128Kx16 and 256Kx16
■ Embedded Erase and Program Algorithms
■ TTL Compatible Inputs and CMOS Outputs
■ Sector Architecture
• 8 equal size sectors of 16KBytes each per chip
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
■ Page Program Operation and Internal Program Control Time
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
■ 100,000 Erase/Program Cycles Minimum (0°C to 70°C)
■ Data Retention, 10 Years at 125°C
Note: Programming information available upon request.
■ Commercial, Industrial and Military Temperature Ranges
FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
PIN DESCRIPTION
V
CC
CS2*/NC
CS1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
WE
A16
A15
A14
A13
A12
A11
A10
A9
2
A0-16
I/O0-15
CS1-2
OE
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
3
4
5
6
7
8
WE
9
I/O8
10
11
12
13
14
15
16
17
18
19
20
VCC
GND
A8
GND
I/O7
GND
A7
I/O6
A6
I/O5
A5
I/O4
A4
I/O3
7
A3
I/O2
BLOCK DIAGRAM
FOR WF256K16-XCX5
A2
I/O1
A1
I/O0
A0
OE
I/O0-7
I/O8-15
* CS2 for 256Kx16 and NC for 128Kx16
WE
OE
BLOCK DIAGRAM
FOR WF128K16-XCX5
A
0-16
I/O0-7
I/O8-15
WE
128K x 8
128K x 8
128K x 8
128K x 8
OE
0-16
A
CS1(1)
CS2(1)
128K x 8
128K x 8
NOTE:
1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the
device. CS1 and CS2 must not be enabled at the same time.
CS
1
October 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520