Datasheet > WF256K16-90CQ5

WF256K16-90CQ5

更新时间： 2024-11-12 20:26:31

品牌	Logo	应用领域
WEDC		内存集成电路
页数	文件大小	规格书
11页	363K
描述
Flash Module, 256KX16, 90ns, CDIP40,

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中文翻译

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数据手册

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WF256K16-90CQ5 数据手册

WF128K16-XCX5

WF256K16-XCX5

PRELIMINARY*

White Electronic Designs

5V FLASH MODULE

FEATURES

ꢀ

Access Times of 50, 60, 70, 90, 120 and 150ns

ꢀ

5 Volt Programming; 5V 10ꢀ Supply

40 pin Ceramic DIP (Package 303)

Organized as 128Kx16 and 256Kx16

Sector Architecture

Low Power CMOS

Embedded Erase and Program Algorithms

TTL Compatible Inputs and CMOS Outputs

• 8 equal size sectors of 16KBytes each per chip

Built-in Decoupling Caps and Multiple Ground Pins

for Low Noise Operation

• Any combination of sectors can be concurrently

erased.

ꢀ

Page Program Operation and Internal Program

Control Time

• Also supports full chip erase

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

ꢀ

100,000 Erase/Program Cycles Minimum (0°C to

70°C)

Note: Programming information available upon request.

ꢀ

Data Retention, 10 Years at 125°C

Commercial, Industrial and Military Temperature

Ranges

FIGURE 1 – PIN CONFIGURATION AND BLOCK DIAGRAM

TOP VIEW

PIN DESCRIPTION

CS2#*/NC

CS#1

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

A0-16

Address Inputs

WE#

A16

A15

A14

A13

A12

A11

A10

GND

I/O0-15 Data Input/Output

CS1-2

Chip Selects

Output Enable

Write Enable

+5.0V Power

Ground

I/O8

GND

I/O7

VCC

GND

I/O6

I/O5

* CS2# for 256Kx16

and NC for 128Kx16

I/O4

I/O3

I/O2

I/O1

I/O0

OE#

BLOCK DIAGRAM

FOR WF256K16-XCX5

I/O0-7

I/O8-15

WE#

OE#

0-16

BLOCK DIAGRAM

FOR WF128K16-XCX5

128K x 8

I/O0-7

I/O8-15

WE#

OE#

A0-16

(1)

128K x 8

NOTE: 1. CS1# and CS2# are used to select the lower and upper

128Kx16 of the device. CS1# and CS2# must not be

enabled at the same time.

CS1#

October 1998

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...11

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