Datasheet > WED3C755E8M300BM

WED3C755E8M300BM

更新时间： 2024-02-23 05:54:02

品牌	Logo	应用领域
WEDC		微处理器
页数	文件大小	规格书
14页	347K
描述
RISC MICROPROCESSOR MULTI-CHIP PACKAGE

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WED3C755E8M300BM 数据手册

WED3C755E8M-XBX

White Electronic Designs

RISC MICROPROCESSOR MULTI-CHIP PACKAGE

OVERVIEW

FEATURES

The WEDC 755E/SSRAM multichip package is targeted

for high performance, space sensitive, low power systems

and supports the following power management features:

doze, nap, sleep and dynamic power management. The

WED3C755E8M-XBX multichip package consists of:

The WED3C755E8M-XBX is offered in Commercial

(0°C to +70°C), industrial (-40°C to +85°C) and military

(-55°C to +125°C) temperature ranges and is well suited

for embedded applications such as missiles, aerospace,

ﬂight computers, ﬁre control systems and rugged critical

systems.

ꢀ

755 RISC processor (E die revision)

ꢀ

Footprint compatible with WED3C7558M-XBX and

WED3C750A8M-200BX

Dedicated 1MB SSRAM L2 cache, conﬁgured as

128Kx72

ꢀ

Footprint compatible with Motorola MPC 745

ꢀ

21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)

Core Frequency/L2 Cache Frequency (300MHz/

150MHz, 350MHz/175MHz)

This product is subject to change without notice.

ꢀ

Maximum 60x Bus frequency = 66MHz

FIG. 1 - MULTI-CHIP PACKAGE DIAGRAM

SSRAM

µP

755E

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

May, 2003

Rev 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...14

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